separate .text and .data for instruction and data memory

hdl/tb/core_tb.v

@@ -4,27 +4,31 @@ module core_tb();
 
 initial $timeformat(-9, 2, " ns", 20);
 
-localparam  MEM_INST_LENGTH = 256;
-localparam  MEM_DATA_LENGTH = 256;
+wire dummy_out;
 
-localparam  INST_NOP = 32'h00000013;  // nop
+localparam  MEM_INST_LENGTH = 256;  // words
+localparam  MEM_DATA_LENGTH = 256;  // words
+
+localparam  INST_NOP        = 32'h00000013;  // nop
+localparam  DATA_DEFAULT    = 32'hdeadbeef;
 
 reg clk, reset;
+
+// Instruction memory
 reg [31:0] mem_inst [0:MEM_INST_LENGTH-1];
 wire [31:0] mem_inst_addr;
 wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
 wire [31:0] mem_inst_data = mem_inst_idx < MEM_INST_LENGTH ? mem_inst[mem_inst_idx] : INST_NOP;
 
-wire dummy_out;
-
 initial begin: mem_inst_init
     integer i;
     for (i=0; i<MEM_INST_LENGTH; i=i+1) begin
         mem_inst[i] = INST_NOP;
     end
-    $readmemh("../test/test.hex", mem_inst);
+    $readmemh("../test/text.hex", mem_inst);
 end
 
+// Data memory
 reg [31:0] mem_data [0:MEM_DATA_LENGTH-1];
 wire [31:0] mem_data_waddr;
 wire [31:0] mem_data_wdata;
@@ -34,6 +38,14 @@ wire [31:0] mem_data_raddr;
 reg [31:0] mem_data_rdata;
 wire [3:0] mem_data_rmask;
 
+initial begin: mem_data_init
+    integer i;
+    for (i=0; i<MEM_DATA_LENGTH; i=i+1) begin
+        mem_data[i] = DATA_DEFAULT;
+    end
+    $readmemh("../test/data.hex", mem_data);
+end
+
 initial begin
     #0
     clk = 0;