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tweak makefile

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Brendan Haines 2021-07-02 04:58:58 -06:00
parent c0852697df
commit b79c572a22
1 changed files with 2 additions and 1 deletions
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Makefile
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@ -40,9 +40,10 @@ $(BUILD_DIR)/%.elf: test/%.ld $(BUILD_DIR)/%.o | $(BUILD_DIR)
%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
sim: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
$(BUILD_DIR)/core_tb.vcd: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
cd $(BUILD_DIR) && ./tb.out
sim: $(BUILD_DIR)/core_tb.vcd
## General
$(BUILD_DIR):