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91
hdl/axi_lite.md Normal file
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```wavedrom
{
signal: [
{name: 'ACLK', wave: 'P..|..'},
['Write Address',
{name: 'AWVALID', wave: '010|..', data: []},
{name: 'AWADDR', wave: 'x3x|..', data: [1,2,3,4]},
{name: 'AWPROT', wave: 'x3x|..', data: [1,2,3,4]},
{name: 'AWREADY', wave: '1..|..', data: []},
],
['Write Data',
{name: 'WVALID', wave: '010|..', data: []},
{name: 'WDATA', wave: 'x3x|..', data: [1,2,3,4]},
{name: 'WSTRB', wave: 'x3x|..', data: [1,2,3,4]},
{name: 'WREADY', wave: '1..|..', data: []},
],
['Write Resp',
{name: 'BVALID', wave: '0..|10', data: []},
{name: 'BREADY', wave: '01.|.0', data: []},
{name: 'BRESP', wave: 'x..|3x', data: [1,2,3,4]},
],
],
head:{
text:'AXI-Lite Write Example',
tick:0,
},
foot:{
text:'Slave may take arbitrarily long to respond',
}
}
```
```wavedrom
{
signal: [
{name: 'ACLK', wave: 'P.......'},
['Write Address',
{name: 'AWVALID', wave: '01...0..', data: []},
{name: 'AWADDR', wave: 'x345.x..', data: [1,2,3,4]},
{name: 'AWPROT', wave: 'x345.x..', data: [1,2,3,4]},
{name: 'AWREADY', wave: '1..01...', data: []},
],
['Write Data',
{name: 'WVALID', wave: '010.1.0.', data: []},
{name: 'WDATA', wave: 'x3x.45x.', data: [1,2,3,4]},
{name: 'WSTRB', wave: 'x3x.45x.', data: [1,2,3,4]},
{name: 'WREADY', wave: '1.......', data: []},
],
['Write Resp',
{name: 'BVALID', wave: '0.10.1.0', data: []},
{name: 'BREADY', wave: '01.....0', data: []},
{name: 'BRESP', wave: 'x.3x.45x', data: [1,2,3,4]},
],
],
head:{
text:'AXI-Lite Write Example',
tick:0,
}
}
```
```wavedrom
{
signal: [
{name: 'ACLK', wave: 'P.....'},
['Write Address',
{name: 'AWVALID', wave: '01..0.', data: []},
{name: 'AWADDR', wave: 'x345x.', data: [1,2,3,4]},
{name: 'AWPROT', wave: 'x345x.', data: [1,2,3,4]},
{name: 'AWREADY', wave: '1...0.', data: []},
],
['Write Data',
{name: 'WVALID', wave: '01..0.', data: []},
{name: 'WDATA', wave: 'x345x.', data: [1,2,3,4]},
{name: 'WSTRB', wave: 'x345x.', data: [1,2,3,4]},
{name: 'WREADY', wave: '1.....', data: []},
],
['Write Resp',
{name: 'BVALID', wave: '0.1..0', data: []},
{name: 'BREADY', wave: '01...0', data: []},
{name: 'BRESP', wave: 'x.345x', data: [1,2,3,4]},
],
],
head:{
text:'AXI-Lite Write Example',
tick:0,
}
}
```

36
hdl/axi_lite_if.sv Normal file
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interface axi_lite();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 12;
// Global
logic ACLK;
logic ARESETn;
// Write address
logic AWVALID;
logic [ADDR_WIDTH-1:0] AWADDR;
logic [2:0] AWPROT;
logic AWREADY;
// Write data
logic WVALID;
logic [DATA_WIDTH-1:0] WDATA;
logic [(DATA_WIDTH/8)-1:0] WSTRB;
logic WREADY;
// Write response
logic BVALID;
logic BREADY;
logic [1:0] BRESP;
// Read address
logic ARVALID;
logic [ADDR_WIDTH-1:0] ARADDR;
logic [2:0] ARPROT;
logic ARREADY;
// Read data
logic RVALID;
logic [DATA_WIDTH-1:0] RDATA;
logic [1:0] RRESP;
logic RREADY;
endinterface

56
hdl/correlator.v Normal file
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module correlator #(
parameter LENGTH = 8,
parameter BITS_IN = 8,
parameter BITS_INTERNAL = BITS_IN + $clog2(LENGTH),
parameter BITS_OUT = 8,
)(
input wire clk,
input wire reset,
input wire [BITS_IN-1:0] a,
input wire [BITS_IN-1:0] b,
output reg [BITS_OUT-1:0] y
);
// verify parameters are valid
if (BITS_OUT > BITS_INTERNAL) begin
$error("BITS_OUT (%d) must be <= BITS_INTERNAL (%d)", BITS_OUT, BITS_INTERNAL);
end
// signals
reg [BITS_IN-1] aa [0:LENGTH-1];
reg [BITS_IN-1] bb [0:LENGTH-1];
reg [BITS_INTERNAL-1:0] sum;
// combinatorial calculation
always @(*) begin : continuous
integer i;
aa[0] = a;
bb[0] = b;
sum = 0;
for (i=0; i<LENGTH; i=i+1) begin
sum = sum + aa[i] * bb[i]
end
end
// synchronous update
always @(posedge clk or posedge reset) begin : update
integer i;
if (reset) begin
for (i=1; i<LENGTH; i=i+1) begin
aa[i] <= 0;
bb[i] <= 0;
end
y <= 0;
end else begin
for (i=1; i<LENGTH; i=i+1) begin
aa[i] <= aa[i-1];
bb[i] <= bb[i-1];
end
y <= sum[BITS_OUT-1:0];
end
end
endmodule

22
hdl/gps.v Normal file
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module gps #(
parameter BITS_IN,
)(
input wire clk,
input wire reset,
input [BITS_IN-1:0] in_i,
input [BITS_IN-1:0] in_q,
);
for (prn=1; prn<=32; prn=prn+1) begin
correlator #(
.BITS_IN(BITS_IN),
) cor(
.clk(clk),
.reset(reset),
.a()
);
end
endmodule

21
hdl/test.sv Normal file
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interface test_if();
parameter int DW = 32;
logic[DW-1:0] data;
modport consumer (
input data
);
endinterface
module test_mod(
test_if.consumer if_in,
output[31:0] dout
);
assign dout = if_in.data;
endmodule

66
hdl/test_sv.sv Normal file
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// `include "axi_lite_if.sv"
interface axi_lite_if();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 12;
logic RREADY;
modport master (
output RREADY
);
modport slave (
// // Global
// input ACLK,
// input ARESETn,
// // Write address
// input AWVALID,
// // input [ADDR_WIDTH-1:0] AWADDR,
// // input [2:0] AWPROT,
// output AWREADY,
// // Write data
// input WVALID,
// // input [DATA_WIDTH-1:0] WDATA,
// // input [(DATA_WIDTH/8)-1:0] WSTRB,
// output WREADY,
// // Write response
// output BVALID,
// input BREADY,
// // output [1:0] BRESP,
// // Read address
// input ARVALID,
// // input [ADDR_WIDTH-1:0] ARADDR,
// // input [2:0] ARPROT,
// output ARREADY,
// // Read data
// output RVALID,
// output [DATA_WIDTH-1:0] RDATA,
// output [1:0] RRESP,
input RREADY
);
endinterface
module test_sv(
axi_lite_if.slave s_axil,
input clk,
output c, d
);
logic a, b;
assign a = clk;
always @(*) begin
b = !clk;
end
assign c = a;
assign d = b;
endmodule