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21 lines
227 B
Systemverilog
21 lines
227 B
Systemverilog
interface test_if();
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parameter int DW = 32;
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logic[DW-1:0] data;
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modport consumer (
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input data
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);
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endinterface
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module test_mod(
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test_if.consumer if_in,
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output[31:0] dout
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);
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assign dout = if_in.data;
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endmodule |