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passes quick test: slli, srli, srai

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Brendan Haines 2020-10-11 23:36:11 -06:00
parent 46a0972803
commit 913ffb3af6
2 changed files with 43 additions and 20 deletions
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10
hdl/core.v
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@ -222,9 +222,9 @@ always @(*) begin
10'b100xxxxxxx: s_id_aluop = ALUOP_XOR; // XORI
10'b110xxxxxxx: s_id_aluop = ALUOP_OR; // ORI
10'b111xxxxxxx: s_id_aluop = ALUOP_AND; // ANDI
10'b0010000000: s_id_aluop = ALUOP_SL; // SLLI
10'b1010000000: s_id_aluop = ALUOP_SRL; // SRLI
10'b1010100000: s_id_aluop = ALUOP_SRA; // SRAI
10'b001000000x: s_id_aluop = ALUOP_SL; // SLLI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
10'b101000000x: s_id_aluop = ALUOP_SRL; // SRLI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
10'b101010000x: s_id_aluop = ALUOP_SRA; // SRAI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
default: begin
s_id_s1 = 32'hxxxxxxxx;
s_id_s2 = 32'hxxxxxxxx;
@ -312,10 +312,10 @@ always @(*) begin
s_ex_alu_out = s_ex_data1 << s_ex_data2;
end
ALUOP_SRL: begin
s_ex_alu_out = s_ex_data1 >> s_ex_data2;
s_ex_alu_out = s_ex_data1 >> s_ex_data2[5:0]; // NOTE: shamt is only 5 bits. Increased for gcc support
end
ALUOP_SRA: begin
s_ex_alu_out = s_ex_data1 >>> s_ex_data2;
s_ex_alu_out = $signed(s_ex_data1) >>> s_ex_data2[5:0]; // NOTE: shamt is only 5 bits. Increased for gcc support
end
ALUOP_SLT: begin
s_ex_alu_out = $signed(s_ex_data1) < $signed(s_ex_data2);

53
test/test.S
View File

@ -8,9 +8,6 @@ _start:
# JAL
# JALR
# SLLI
# SRLI
# SRAI
# SLTI
# SLTUI
@ -21,43 +18,43 @@ _start:
# SLTU
# lui
lui x1, 0xfedcb # x1 = 0xfedcb000
lui x1, 0xfedcb # x1 = 0xfedcb000
nop
nop
nop
# addi
addi x1, x1, 0x789 # x1 = 0xfedcb789
addi x2, x0, -1 # x2 = 0xffffffff
addi x1, x1, 0x789 # x1 = 0xfedcb789
addi x2, x0, -1 # x2 = 0xffffffff
nop
nop
addi x3, x1, -0x777 # x3 = 0xfedcb012
addi x3, x1, -0x777 # x3 = 0xfedcb012
nop
nop
nop
# add
add x4, x1, x2 # x4 = 0xfedcb788
add x4, x1, x2 # x4 = 0xfedcb788
nop
nop
nop
# sub
sub x5, x1, x3 # x5 = 0x00000777
sub x5, x1, x3 # x5 = 0x00000777
nop
nop
nop
# and
and x6, x1, x2 # x6 = 0xfedcb789
and x7, x1, x0 # x7 = 0x00000000
and x8, x4, x3 # x8 = 0xfedcb000
and x6, x1, x2 # x6 = 0xfedcb789
and x7, x1, x0 # x7 = 0x00000000
and x8, x4, x3 # x8 = 0xfedcb000
nop
nop
nop
# or
or x9, x1, x2 # x9 = 0xffffffff
or x9, x1, x2 # x9 = 0xffffffff
or x10, x1, x0 # x10 = 0xfedcb789
or x11, x4, x3 # x11 = 0x0xfedcb79a
nop
@ -96,18 +93,44 @@ _start:
nop
nop
# slli
slli x24, x23, 4 # x24 = 0x00007880
slli x25, x2, 1 # x25 = 0xfffffffe
slli x26, x2, 63 # x26 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
slli x27, x2, 31 # x27 = 0x80000000
nop
nop
nop
# srli
srli x28, x23, 4 # x28 = 0x00000078
srli x29, x2, 1 # x29 = 0x7fffffff
srli x30, x2, 63 # x30 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
srli x3, x2, 31 # x3 = 0x00000001
nop
nop
nop
# srai
srai x4, x23, 4 # x4 = 0x00000078 // fails
srai x5, x2, 1 # x5 = 0xffffffff
srai x6, x2, 63 # x6 = 0xffffffff // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
srai x7, x2, 31 # x7 = 0xffffffff
nop
nop
nop
# counter and infinite loop
nop
nop
nop
addi x31, x0, 1 # x1 = 1
addi x31, x0, 1 # x1 = 1
loop:
nop
nop
nop
addi x31, x31, 1 # increment x1
addi x31, x31, 1 # increment x1
nop
nop
nop