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update tests

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This commit is contained in:
Brendan Haines 2021-09-09 00:06:15 -06:00
parent 8901e538e1
commit 625001152d
4 changed files with 7 additions and 6 deletions
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1
testbench/test_basic/Makefile
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@ -12,7 +12,6 @@ OBJ += $(notdir $(SOURCE_C:.c=.o))
CC = riscv64-linux-gnu-gcc CC = riscv64-linux-gnu-gcc
CFLAGS = -march=rv32i -mabi=ilp32 CFLAGS = -march=rv32i -mabi=ilp32
# -static -ffreestanding
CPPFLAGS = CPPFLAGS =

2
testbench/test_basic/tb.sv
View File

@ -13,7 +13,7 @@ initial begin: dump
// for (i=0; i<32; i=i+1) begin // for (i=0; i<32; i=i+1) begin
// $dumpvars(0, dut.regfile[i]); // $dumpvars(0, dut.regfile[i]);
// end // end
$dumpvars(0, mem[ADDR_FAILCODE]); // $dumpvars(0, mem[ADDR_FAILCODE]);
end end
reg clk, reset; reg clk, reset;

8
testbench/test_c/Makefile
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@ -6,22 +6,24 @@ SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
LOGS = $(TESTBENCH_V:.sv=.log) LOGS = $(TESTBENCH_V:.sv=.log)
SOURCE_C = $(wildcard *.c) SOURCE_C = $(wildcard *.c)
# SOURCE_C =
SOURCE_AS = $(wildcard *.S) SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o)) OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o)) OBJ += $(notdir $(SOURCE_C:.c=.o))
CC = riscv64-linux-gnu-gcc CC = riscv64-linux-gnu-gcc
CFLAGS = -march=rv32i -mabi=ilp32 CFLAGS = -march=rv32i -mabi=ilp32
# -static -ffreestanding # CFLAGS = -march=rv64i -mabi=lp64
# CFLAGS += -nostdlib -lgcc
CPPFLAGS = CPPFLAGS =
AS = riscv64-linux-gnu-as AS = riscv64-linux-gnu-as
ASFLAGS = -march=rv32i -mabi=ilp32 ASFLAGS = -march=rv32i -mabi=ilp32
# ASFLAGS = -march=rv64i -mabi=lp64
LD = riscv64-linux-gnu-ld LD = riscv64-linux-gnu-ld
LDFLAGS = -melf32lriscv_ilp32 LDFLAGS = -melf32lriscv_ilp32
# LDFLAGS =
# $(info $$TESTBENCH_V is [${TESTBENCH_V}]) # $(info $$TESTBENCH_V is [${TESTBENCH_V}])
@ -37,7 +39,7 @@ LDFLAGS = -melf32lriscv_ilp32
%.o: %.c %.o: %.c
%.s: %.c %.s: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -S $^ -o $@ $(CC) $(CFLAGS) -S $^ -o $@
%.elf: %.ld $(OBJ) %.elf: %.ld $(OBJ)
$(LD) $(LDFLAGS) -T $^ -o $@ $(LD) $(LDFLAGS) -T $^ -o $@

2
testbench/test_c/tb.sv
View File

@ -13,7 +13,7 @@ initial begin: dump
// for (i=0; i<32; i=i+1) begin // for (i=0; i<32; i=i+1) begin
// $dumpvars(0, dut.regfile[i]); // $dumpvars(0, dut.regfile[i]);
// end // end
$dumpvars(0, mem[ADDR_FAILCODE]); // $dumpvars(0, mem[ADDR_FAILCODE]);
end end
reg clk, reset; reg clk, reset;