formatting

This commit is contained in:
Brendan Haines 2022-12-01 01:07:15 -07:00
parent f12d3be0bd
commit 5d3d9b222f
3 changed files with 145 additions and 150 deletions

View File

@ -1,24 +1,23 @@
`timescale 1ns/1ps
package bh_assert;
int bh_assert_pass_count = 0;
int bh_assert_fail_count = 0;
int bh_assert_warn_count = 0;
int bh_assert_pass_count = 0;
int bh_assert_fail_count = 0;
int bh_assert_warn_count = 0;
localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
localparam COLOR_RED = "\033[31m";
localparam COLOR_YELLOW = "\033[33m";
localparam COLOR_GREEN = "\033[32m";
localparam COLOR_NORMAL = "\033[0;39m";
localparam COLOR_RED = "\033[31m";
localparam COLOR_YELLOW = "\033[33m";
localparam COLOR_GREEN = "\033[32m";
localparam COLOR_NORMAL = "\033[0;39m";
task bh_assert_equal(int val, int expected, string description);
task bh_assert_equal(int val, int expected, string description);
// display results
$timeformat(-9, 2, " ns", 20);
$display(
@ -37,9 +36,9 @@ task bh_assert_equal(int val, int expected, string description);
end else begin
bh_assert_fail_count = bh_assert_fail_count + 1;
end
endtask
endtask
task bh_assert_stats;
task bh_assert_stats;
$timeformat(-9, 2, " ns", 20);
$display("%t: DONE: %1d pass, %1d fail, %1d warn", $time, bh_assert_pass_count, bh_assert_fail_count, bh_assert_warn_count);
if (bh_assert_pass_count + bh_assert_fail_count == 0) begin
@ -50,20 +49,19 @@ task bh_assert_stats;
end else begin
$display("%sSUCCESS%s: all tests passed", COLOR_GREEN, COLOR_NORMAL);
end
endtask
endtask
task bh_info(string description);
task bh_info(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_INFO) begin
$display("%t: INFO: %s", $time, description);
end
endtask
endtask
task bh_warn(string description);
task bh_warn(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_WARN) begin
$display("%t: %sWARN%s: %s", $time, COLOR_YELLOW, COLOR_NORMAL, description);
end
bh_assert_warn_count = bh_assert_warn_count + 1;
endtask
endtask
endpackage

View File

@ -12,11 +12,10 @@ module skidbuffer #(
output logic out_valid,
input logic out_ready
);
logic buffer_filled = 0;
logic [WIDTH-1:0] buffer_val;
logic buffer_filled = 0;
logic [WIDTH-1:0] buffer_val;
always_ff @(posedge clk) begin
always_ff @(posedge clk) begin
if (reset) begin
buffer_filled <= 0;
end else begin
@ -37,9 +36,9 @@ always_ff @(posedge clk) begin
end
end
end
end
end
always_comb begin
always_comb begin
if (buffer_filled) begin
in_ready = out_ready;
out_valid = 1;
@ -49,6 +48,6 @@ always_comb begin
out_valid = in_valid;
out = in;
end
end
end
endmodule

View File

@ -5,22 +5,21 @@ import bh_assert::bh_assert_equal;
import bh_assert::bh_assert_stats;
module skidbuffer_tb();
parameter WIDTH = 15;
parameter TEST_LIST_LENGTH = 256;
parameter WIDTH = 15;
parameter TEST_LIST_LENGTH = 256;
logic clk = 0;
logic reset = 1;
logic [WIDTH-1:0] in;
logic in_valid = 0;
wire in_ready;
wire [WIDTH-1:0] out;
wire out_valid;
logic out_ready = 0;
logic clk = 0;
logic reset = 1;
logic [WIDTH-1:0] in;
logic in_valid = 0;
wire in_ready;
wire [WIDTH-1:0] out;
wire out_valid;
logic out_ready = 0;
skidbuffer #(
skidbuffer #(
.WIDTH(WIDTH)
) dut (
) dut (
.clk(clk),
.reset(reset),
.in(in),
@ -29,18 +28,18 @@ skidbuffer #(
.out(out),
.out_valid(out_valid),
.out_ready(out_ready)
);
);
integer i = 0;
integer in_count = 0;
integer out_count = 0;
logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
integer i = 0;
integer in_count = 0;
integer out_count = 0;
logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
assign in = in_list[in_count];
assign in = in_list[in_count];
always #5 clk = !clk;
always #5 clk = !clk;
initial begin
initial begin
$dumpfile("skidbuffer_tb.vcd");
$dumpvars(0, skidbuffer_tb);
@ -63,9 +62,9 @@ initial begin
bh_assert_stats();
$finish;
end
end
always @(posedge clk) begin
always @(posedge clk) begin
if (reset == 0 && in_valid && in_ready) begin
in_count <= in_count + 1;
end
@ -74,10 +73,9 @@ always @(posedge clk) begin
bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
out_count <= out_count + 1;
end
end
wire [WIDTH-1:0] out_correct;
assign out_correct = in_list[out_count];
end
wire [WIDTH-1:0] out_correct;
assign out_correct = in_list[out_count];
endmodule