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@ -1,7 +1,6 @@
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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package bh_assert;
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package bh_assert;
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int bh_assert_pass_count = 0;
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int bh_assert_pass_count = 0;
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int bh_assert_fail_count = 0;
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int bh_assert_fail_count = 0;
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int bh_assert_warn_count = 0;
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int bh_assert_warn_count = 0;
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@ -65,5 +64,4 @@ task bh_warn(string description);
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bh_assert_warn_count = bh_assert_warn_count + 1;
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bh_assert_warn_count = bh_assert_warn_count + 1;
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endtask
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endtask
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endpackage
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endpackage
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@ -12,7 +12,6 @@ module skidbuffer #(
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output logic out_valid,
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output logic out_valid,
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input logic out_ready
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input logic out_ready
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);
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);
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logic buffer_filled = 0;
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logic buffer_filled = 0;
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logic [WIDTH-1:0] buffer_val;
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logic [WIDTH-1:0] buffer_val;
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@ -5,7 +5,6 @@ import bh_assert::bh_assert_equal;
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import bh_assert::bh_assert_stats;
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import bh_assert::bh_assert_stats;
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module skidbuffer_tb();
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module skidbuffer_tb();
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parameter WIDTH = 15;
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parameter WIDTH = 15;
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parameter TEST_LIST_LENGTH = 256;
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parameter TEST_LIST_LENGTH = 256;
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@ -79,5 +78,4 @@ end
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wire [WIDTH-1:0] out_correct;
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wire [WIDTH-1:0] out_correct;
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assign out_correct = in_list[out_count];
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assign out_correct = in_list[out_count];
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endmodule
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endmodule
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