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fix issue of jumping to address 0

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This commit is contained in:
Brendan Haines
2020-11-14 23:04:24 -07:00
parent caf9a6f4f7
commit 4a25ca6def
7 changed files with 213 additions and 154 deletions
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154
hdl/tb/core_tb.v
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@ -10,7 +10,8 @@ localparam MEM_INST_LENGTH = 256; // words
localparam MEM_DATA_LENGTH = 256; // words
localparam INST_NOP = 32'h00000013; // nop
localparam DATA_DEFAULT = 32'hdeadbeef;
localparam DATA_DEFAULT = 32'h00000000;
localparam DATA_INVALID = 32'hdeadbeef;
reg clk, reset;
@ -30,13 +31,11 @@ end
// Data memory
reg [31:0] mem_data [0:MEM_DATA_LENGTH-1];
wire [31:0] mem_data_waddr;
wire [31:0] mem_data_addr;
reg [31:0] mem_data_rdata;
wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
wire [31:0] mem_data_raddr;
reg [31:0] mem_data_rdata;
wire [3:0] mem_data_rmask;
initial begin: mem_data_init
integer i;
@ -54,7 +53,7 @@ initial begin
#10
reset = 0;
#1000
#2000
reset = 1;
$stop;
end
@ -68,6 +67,12 @@ core dut(
.mem_inst_addr(mem_inst_addr),
.mem_inst_data(mem_inst_data),
.mem_data_addr(mem_data_addr),
.mem_data_rdata(mem_data_rdata),
.mem_data_wdata(mem_data_wdata),
.mem_data_wmask(mem_data_wmask),
.mem_data_we(mem_data_we),
// .mem_data_addr(mem_data_addr),
// .mem_data_wdata(mem_data_wdata),
// .mem_data_rdata(mem_data_rdata),
@ -79,81 +84,84 @@ core dut(
.dummy_out(dummy_out)
);
wire axi_mem_data_awvalid;
wire [11:0] axi_mem_data_awaddr;
wire [2:0] axi_mem_data_awprot;
wire axi_mem_data_awready;
wire axi_mem_data_wvalid;
wire [31:0] axi_mem_data_wdata;
wire [3:0] axi_mem_data_wstrb;
wire axi_mem_data_wready;
wire axi_mem_data_bvalid;
wire axi_mem_data_bready;
wire [1:0] axi_mem_data_bresp;
wire axi_mem_data_arvalid;
wire [11:0] axi_mem_data_araddr;
wire [2:0] axi_mem_data_arprot;
wire axi_mem_data_arready;
wire axi_mem_data_rvalid;
wire [31:0] axi_mem_data_rdata;
wire [1:0] axi_mem_data_resp;
wire axi_mem_data_rready;
// wire axi_mem_data_awvalid;
// wire [11:0] axi_mem_data_awaddr;
// wire [2:0] axi_mem_data_awprot;
// wire axi_mem_data_awready;
// wire axi_mem_data_wvalid;
// wire [31:0] axi_mem_data_wdata;
// wire [3:0] axi_mem_data_wstrb;
// wire axi_mem_data_wready;
// wire axi_mem_data_bvalid;
// wire axi_mem_data_bready;
// wire [1:0] axi_mem_data_bresp;
// wire axi_mem_data_arvalid;
// wire [11:0] axi_mem_data_araddr;
// wire [2:0] axi_mem_data_arprot;
// wire axi_mem_data_arready;
// wire axi_mem_data_rvalid;
// wire [31:0] axi_mem_data_rdata;
// wire [1:0] axi_mem_data_resp;
// wire axi_mem_data_rready;
axi_lite_memory axi_mem_data(
.ACLK(clk),
.ARESETn(!reset),
.AWVALID(axi_mem_data_awvalid),
.AWADDR(axi_mem_data_awaddr),
.AWPROT(axi_mem_data_awprot),
.AWREADY(axi_mem_data_awready),
.WVALID(axi_mem_data_wvalid),
.WDATA(axi_mem_data_wdata),
.WSTRB(axi_mem_data_wstrb),
.WREADY(axi_mem_data_wready),
.BVALID(axi_mem_data_bvalid),
.BREADY(axi_mem_data_bready),
.BRESP(axi_mem_data_bresp),
.ARVALID(axi_mem_data_arvalid),
.ARADDR(axi_mem_data_araddr),
.ARPROT(axi_mem_data_arprot),
.ARREADY(axi_mem_data_arready),
.RVALID(axi_mem_data_rvalid),
.RDATA(axi_mem_data_rdata),
.RRESP(axi_mem_data_resp),
.RREADY(axi_mem_data_rready),
// axi_lite_memory axi_mem_data(
// .ACLK(clk),
// .ARESETn(!reset),
// .AWVALID(axi_mem_data_awvalid),
// .AWADDR(axi_mem_data_awaddr),
// .AWPROT(axi_mem_data_awprot),
// .AWREADY(axi_mem_data_awready),
// .WVALID(axi_mem_data_wvalid),
// .WDATA(axi_mem_data_wdata),
// .WSTRB(axi_mem_data_wstrb),
// .WREADY(axi_mem_data_wready),
// .BVALID(axi_mem_data_bvalid),
// .BREADY(axi_mem_data_bready),
// .BRESP(axi_mem_data_bresp),
// .ARVALID(axi_mem_data_arvalid),
// .ARADDR(axi_mem_data_araddr),
// .ARPROT(axi_mem_data_arprot),
// .ARREADY(axi_mem_data_arready),
// .RVALID(axi_mem_data_rvalid),
// .RDATA(axi_mem_data_rdata),
// .RRESP(axi_mem_data_resp),
// .RREADY(axi_mem_data_rready),
.WB_WADDR(mem_data_waddr),
.WB_WPROT(),
.WB_WDATA(mem_data_wdata),
.WB_WSTRB(mem_data_wmask),
.WB_WVALID(mem_data_we),
.WB_WREADY(1'b1),
// .WB_WADDR(mem_data_waddr),
// .WB_WPROT(),
// .WB_WDATA(mem_data_wdata),
// .WB_WSTRB(mem_data_wmask),
// .WB_WVALID(mem_data_we),
// .WB_WREADY(1'b1),
.WB_RADDR(mem_data_raddr),
.WB_RDATA(mem_data_rdata),
.WB_RVALID(1'b1),
.WB_RREADY()
);
// .WB_RADDR(mem_data_raddr),
// .WB_RDATA(mem_data_rdata),
// .WB_RVALID(1'b1),
// .WB_RREADY()
// );
wire [31:0] mem_data_widx = mem_data_waddr >> 2;
wire [31:0] mem_data_idx = mem_data_addr >> 2;
always @(posedge clk) begin
if (mem_data_we) begin
if (mem_data_widx < MEM_DATA_LENGTH) begin
mem_inst[mem_data_widx] <= (mem_inst[mem_data_widx] & ~{{8{mem_data_wmask[3]}}, {8{mem_data_wmask[2]}}, {8{mem_data_wmask[1]}}, {8{mem_data_wmask[0]}}}) | (mem_data_wdata & {{8{mem_data_wmask[3]}}, {8{mem_data_wmask[2]}}, {8{mem_data_wmask[1]}}, {8{mem_data_wmask[0]}}});
if (mem_data_idx < MEM_DATA_LENGTH) begin
mem_data_rdata = mem_data[mem_data_idx];
if (mem_data_we) begin
if (mem_data_wmask[0]) begin
mem_data[mem_data_idx][7:0] <= mem_data_wdata[7:0];
end
if (mem_data_wmask[1]) begin
mem_data[mem_data_idx][15:8] <= mem_data_wdata[15:8];
end
if (mem_data_wmask[2]) begin
mem_data[mem_data_idx][23:16] <= mem_data_wdata[23:16];
end
if (mem_data_wmask[3]) begin
mem_data[mem_data_idx][31:24] <= mem_data_wdata[31:24];
end
end
end else begin
mem_data_rdata = DATA_INVALID;
// ignore illegal writes
end
end
wire [31:0] mem_data_ridx = mem_data_raddr >> 2;
always @(*) begin
if (mem_data_ridx < MEM_DATA_LENGTH) begin
mem_data_rdata = mem_inst[mem_data_ridx] & {{8{mem_data_rmask[3]}}, {8{mem_data_rmask[2]}}, {8{mem_data_rmask[1]}}, {8{mem_data_rmask[0]}}};
end else begin
mem_data_rdata = 32'h00000000;
end
end
endmodule