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Brendan Haines 2025-09-03 21:51:24 -06:00
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# RISC-V CPU # RISC-V CPU
Short Term To Do: Short Term To Do:
- [ ] add stalls for memory access - [ ] add stalls for memory access
- [ ] use AXI for memory access (depends on AXIL memory module for test) - [ ] use AXI for memory access (depends on AXIL memory module for test)