RISC-V CPU

Short Term To Do:

• add stalls for memory access
• use AXI for memory access (depends on AXIL memory module for test)
• add tests for non-pipelined case
• get C working (may depend on memory stalls)

Desired features:

• 1- or 5-stage pipeline selectable via parameter
• AXI-lite Master for both instruction and data memory
• 32, 64, (or 128?) bit word size
• floating point
• multiplication
• division
• instruction and data caches
• JTAG debug probe

Development

Testing

I'm using act for local testing. No special installation is required since everything gets built and tested in containers as part of the CI actions.

To run the tests, use

act push

Resources

• AXI4 Protocol Specification
• JTAG Bus Description
• 1149.1-2013 - IEEE Standard for Test Access Port and Boundary-Scan Architecture

Attribution

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