works with 8bit addressed memory (rather than word addressed)

This commit is contained in:
2021-07-02 04:22:33 -06:00
parent 57e745b336
commit 35423ce4af
5 changed files with 59 additions and 38 deletions

View File

@ -1,15 +1,15 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 09:22:29 2021
[*] Fri Jul 2 10:10:54 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Fri Jul 2 09:19:55 2021"
[dumpfile_size] 709401
[dumpfile_mtime] "Fri Jul 2 10:09:55 2021"
[dumpfile_size] 53841
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 0
[size] 1920 1052
[pos] -1 -1
*-20.000000 438000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-13.000000 12780 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289
@ -105,7 +105,6 @@ core_tb.dut.\regfile[27][31:0]
core_tb.dut.\regfile[28][31:0]
core_tb.dut.\regfile[29][31:0]
core_tb.dut.\regfile[30][31:0]
@23
core_tb.dut.\regfile[31][31:0]
@200
-
@ -153,6 +152,11 @@ core_tb.dut.r_id_valid
@22
core_tb.dut.r_id_pc[31:0]
core_tb.dut.r_id_inst[31:0]
core_tb.dut.s_id_immed_btype[31:0]
core_tb.dut.s_id_immed_itype[31:0]
core_tb.dut.s_id_immed_jtype[31:0]
core_tb.dut.s_id_immed_stype[31:0]
core_tb.dut.s_id_immed_utype[31:0]
@200
-
@28
@ -165,6 +169,10 @@ core_tb.dut.r_ex_rs1[4:0]
core_tb.dut.r_ex_rs2[4:0]
core_tb.dut.r_ex_rd[4:0]
@22
core_tb.dut.r_ex_s1[31:0]
@23
core_tb.dut.r_ex_s2[31:0]
@22
core_tb.dut.r_ex_aluop[3:0]
@28
core_tb.dut.r_ex_jump

View File

@ -16,18 +16,27 @@ reg clk, reset;
wire dummy_out;
// Memory Parameters
localparam MEM_ROM_LENGTH = 2048 >> 2; // words
localparam MEM_LENGTH = MEM_ROM_LENGTH + 2048 >> 2; // words
localparam MEM_ROM_LENGTH = 2048; // bytes
localparam MEM_LENGTH = MEM_ROM_LENGTH + 2048; // bytes
localparam DATA_INVALID = 32'hdeadbeef;
// Memory
reg [31:0] mem [0:MEM_LENGTH-1];
initial $readmemh("text.hex", mem);
reg [7:0] mem [0:MEM_LENGTH-1];
initial $readmemh("test.hex", mem);
// Instruction Memory
wire [31:0] mem_inst_addr;
wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
wire [31:0] mem_inst_data = mem_inst_idx < MEM_LENGTH ? mem[mem_inst_idx] : DATA_INVALID;
reg [31:0] mem_inst_data;
always @(*) begin
if (mem_inst_addr < MEM_LENGTH - 3) begin
mem_inst_data[ 7: 0] = mem[mem_inst_addr+0];
mem_inst_data[15: 8] = mem[mem_inst_addr+1];
mem_inst_data[23:16] = mem[mem_inst_addr+2];
mem_inst_data[31:24] = mem[mem_inst_addr+3];
end else begin
mem_inst_data = DATA_INVALID;
end
end
// Data memory
wire [31:0] mem_data_addr;
@ -37,26 +46,26 @@ wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
always @(posedge clk) begin
if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
if (mem_data_we) begin
if (mem_data_wmask[0]) begin
mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
end
if (mem_data_wmask[1]) begin
mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
end
if (mem_data_wmask[2]) begin
mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
end
if (mem_data_wmask[3]) begin
mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
end
end
end else begin
// ignore illegal writes
end
end
// always @(posedge clk) begin
// if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
// if (mem_data_we) begin
// if (mem_data_wmask[0]) begin
// mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
// end
// if (mem_data_wmask[1]) begin
// mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
// end
// if (mem_data_wmask[2]) begin
// mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
// end
// if (mem_data_wmask[3]) begin
// mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
// end
// end
// end else begin
// // ignore illegal writes
// end
// end
// Main control