passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
This commit is contained in:
188
hdl/core.v
188
hdl/core.v
@ -1,23 +1,77 @@
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module core(
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input clk,
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input reset,
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output dummy_out,
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output reg [31:0] mem_inst_addr,
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input [31:0] mem_inst_data,
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output reg [31:0] mem_data_addr,
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output reg [31:0] mem_data_wdata,
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input [31:0] mem_data_rdata,
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output reg mem_data_en,
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output reg mem_data_we,
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input mem_data_valid,
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input mem_data_done
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// output reg [31:0] mem_data_addr,
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// output reg [31:0] mem_data_wdata,
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// input [31:0] mem_data_rdata,
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// output reg mem_data_en,
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// output reg mem_data_we,
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// input mem_data_valid,
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// input mem_data_done
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// // instruction memory
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// output axi_inst_ACLK,
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// output axi_inst_ARESETn,
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// output axi_inst_AWVALID,
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// output axi_inst_AWADDR,
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// output [2:0] axi_inst_AWPROT,
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// input axi_inst_AWREADY,
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// output axi_inst_WVALID,
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// output [DATA_WIDTH-1:0] axi_inst_WDATA,
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// output [(DATA_WIDTH/8)-1:0] axi_inst_WSTRB,
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// input axi_inst_WREADY,
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// input axi_inst_BVALID,
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// output axi_inst_BREADY,
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// input [1:0] axi_inst_BRESP,
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// output axi_inst_ARVALID,
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// output axi_inst_ARADDR,
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// output [2:0] axi_inst_ARPROT,
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// input axi_inst_ARREADY,
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// input axi_inst_RVALID,
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// input [DATA_WIDTH-1:0] axi_inst_RDATA,
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// input [1:0] axi_inst_RRESP,
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// output axi_inst_RREADY,
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// data memory
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// output axi_data_ACLK,
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// output axi_data_ARESETn,
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// output axi_data_AWVALID,
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// output axi_data_AWADDR,
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// output [2:0] axi_data_AWPROT,
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// input axi_data_AWREADY,
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// output axi_data_WVALID,
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// output [DATA_WIDTH-1:0] axi_data_WDATA,
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// output [(DATA_WIDTH/8)-1:0] axi_data_WSTRB,
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// input axi_data_WREADY,
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// input axi_data_BVALID,
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// output axi_data_BREADY,
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// input [1:0] axi_data_BRESP,
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// output axi_data_ARVALID,
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// output axi_data_ARADDR,
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// output [2:0] axi_data_ARPROT,
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// input axi_data_ARREADY,
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// input axi_data_RVALID,
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// input [DATA_WIDTH-1:0] axi_data_RDATA,
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// input [1:0] axi_data_RRESP,
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// output axi_data_RREADY,
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output dummy_out
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);
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// Register File
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reg [31:0] regfile [0:31];
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initial regfile[0] = 32'h00000000;
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initial begin : init_regfile
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integer i;
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for (i=0; i<32; i=i+1) begin
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regfile[i] = 32'h00000000;
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end
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end
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// Registers
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reg [31:0] r_if_pc = 0, r_id_pc, r_ex_pc, r_mem_pc, r_wb_pc;
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@ -25,7 +79,7 @@ reg r_id_stall, r_ex_stall, r_mem_stall, r_wb_stall;
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reg [31:0] r_id_inst, r_ex_inst, r_mem_inst, r_wb_inst;
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reg [4:0] r_ex_rd, r_mem_rd, r_wb_rd;
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reg r_ex_alu_seed;
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reg [2:0] r_ex_aluop;
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reg [3:0] r_ex_aluop;
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reg [31:0] r_ex_s1, r_ex_s2, r_mem_s1, r_mem_s2;
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reg [31:0] r_mem_alu_out, r_wb_alu_out;
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reg r_mem_alu_zero;
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@ -62,7 +116,7 @@ reg [6:0] s_id_funct7;
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reg [4:0] s_id_rd, s_id_rs1, s_id_rs2;
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reg [31:0] s_id_immed_itype, s_id_immed_stype, s_id_immed_utype, s_id_immed_btype, s_id_immed_jtype;
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reg [31:0] s_id_s1, s_id_s2;
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reg [2:0] s_id_aluop;
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reg [3:0] s_id_aluop;
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reg s_id_alu_seed;
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reg s_id_invalid;
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reg s_id_jump, s_id_branch;
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@ -87,14 +141,16 @@ localparam OP_LUI = 7'b0110111,
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// TODO: add opcodes for other extensions
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// ALU OPCODES
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localparam ALUOP_ADD = 0,
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ALUOP_XOR = 1,
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ALUOP_OR = 2,
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ALUOP_AND = 3,
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ALUOP_SL = 4,
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ALUOP_SR = 5,
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ALUOP_SLT = 6,
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ALUOP_SLTU = 7;
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localparam ALUOP_ADD = 4'b0000,
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ALUOP_SUB = 4'b0001,
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ALUOP_XOR = 4'b0010,
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ALUOP_OR = 4'b0011,
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ALUOP_AND = 4'b0100,
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ALUOP_SL = 4'b0101,
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ALUOP_SRL = 4'b0110,
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ALUOP_SRA = 4'b0111,
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ALUOP_SLT = 4'b1000,
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ALUOP_SLTU = 4'b1001;
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always @(*) begin
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@ -117,35 +173,31 @@ always @(*) begin
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s_id_immed_jtype = {{11{r_id_inst[31]}}, r_id_inst[31], r_id_inst[19:12], r_id_inst[20], r_id_inst[30:21], 1'b0};
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case (s_id_opcode)
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OP_LUI: begin
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OP_LUI: begin // LUI
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s_id_s1 = 32'h00000000;
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s_id_s2 = s_id_immed_utype;
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s_id_aluop = ALUOP_ADD;
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s_id_alu_seed = 0;
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s_id_jump = 0;
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s_id_branch = 0;
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end
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OP_AUIPC: begin
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OP_AUIPC: begin // AUIPC
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s_id_s1 = r_id_pc;
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s_id_s2 = s_id_immed_utype;
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s_id_aluop = ALUOP_ADD;
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s_id_alu_seed = 0;
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s_id_jump = 0;
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s_id_branch = 0;
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end
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OP_JAL: begin
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OP_JAL: begin // JAL
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s_id_s1 = r_id_pc;
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s_id_s2 = s_id_immed_jtype;
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s_id_aluop = ALUOP_ADD;
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s_id_alu_seed = 0;
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s_id_jump = 1;
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s_id_branch = 0;
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end
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OP_JALR: begin
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OP_JALR: begin // JALR
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = s_id_immed_itype;
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s_id_aluop = ALUOP_ADD;
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s_id_alu_seed = 0;
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s_id_jump = 1;
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s_id_branch = 0;
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end
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@ -164,15 +216,15 @@ always @(*) begin
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s_id_jump = 0;
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s_id_branch = 0;
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casex ({s_id_funct3, s_id_funct7})
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10'b000xxxxxxx: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b0; end // ADDI
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10'b010xxxxxxx: begin s_id_aluop = ALUOP_SLT; s_id_alu_seed = 1'bx; end // SLTI
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10'b011xxxxxxx: begin s_id_aluop = ALUOP_SLTU; s_id_alu_seed = 1'bx; end // SLTUI
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10'b100xxxxxxx: begin s_id_aluop = ALUOP_XOR; s_id_alu_seed = 1'bx; end // XORI
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10'b110xxxxxxx: begin s_id_aluop = ALUOP_OR; s_id_alu_seed = 1'bx; end // ORI
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10'b111xxxxxxx: begin s_id_aluop = ALUOP_AND; s_id_alu_seed = 1'bx; end // ANDI
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10'b0010000000: begin s_id_aluop = ALUOP_SL; s_id_alu_seed = 1'bx; end // SLLI
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10'b1010000000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b0; end // SRLI
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10'b1010100000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b1; end // SRAI
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10'b000xxxxxxx: s_id_aluop = ALUOP_ADD; // ADDI
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10'b010xxxxxxx: s_id_aluop = ALUOP_SLT; // SLTI
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10'b011xxxxxxx: s_id_aluop = ALUOP_SLTU; // SLTUI
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10'b100xxxxxxx: s_id_aluop = ALUOP_XOR; // XORI
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10'b110xxxxxxx: s_id_aluop = ALUOP_OR; // ORI
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10'b111xxxxxxx: s_id_aluop = ALUOP_AND; // ANDI
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10'b0010000000: s_id_aluop = ALUOP_SL; // SLLI
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10'b1010000000: s_id_aluop = ALUOP_SRL; // SRLI
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10'b1010100000: s_id_aluop = ALUOP_SRA; // SRAI
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default: begin
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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@ -186,16 +238,16 @@ always @(*) begin
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s_id_jump = 0;
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s_id_branch = 0;
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case ({s_id_funct3, s_id_funct7})
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10'b0000000000: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b0; end // ADD
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10'b0000100000: begin s_id_aluop = ALUOP_ADD; s_id_alu_seed = 1'b1; end // SUB
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10'b0010000000: begin s_id_aluop = ALUOP_SL; s_id_alu_seed = 1'bx; end // SLL
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10'b0100000000: begin s_id_aluop = ALUOP_SLT; s_id_alu_seed = 1'bx; end // SLT
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10'b0110000000: begin s_id_aluop = ALUOP_SLTU; s_id_alu_seed = 1'bx; end // SLTU
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10'b1000000000: begin s_id_aluop = ALUOP_XOR; s_id_alu_seed = 1'bx; end // XOR
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10'b1100000000: begin s_id_aluop = ALUOP_OR; s_id_alu_seed = 1'bx; end // OR
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10'b1110000000: begin s_id_aluop = ALUOP_AND; s_id_alu_seed = 1'bx; end // AND
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10'b1010000000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b0; end // SRL
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10'b1010100000: begin s_id_aluop = ALUOP_SR; s_id_alu_seed = 1'b1; end // SRA
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10'b0000000000: s_id_aluop = ALUOP_ADD; // ADD
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10'b0000100000: s_id_aluop = ALUOP_SUB; // SUB
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10'b0010000000: s_id_aluop = ALUOP_SL; // SLL
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10'b0100000000: s_id_aluop = ALUOP_SLT; // SLT
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10'b0110000000: s_id_aluop = ALUOP_SLTU; // SLTU
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10'b1000000000: s_id_aluop = ALUOP_XOR; // XOR
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10'b1100000000: s_id_aluop = ALUOP_OR; // OR
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10'b1110000000: s_id_aluop = ALUOP_AND; // AND
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10'b1010000000: s_id_aluop = ALUOP_SRL; // SRL
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10'b1010100000: s_id_aluop = ALUOP_SRA; // SRA
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default: begin
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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@ -219,7 +271,7 @@ always @(*) begin
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endcase
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if (s_id_invalid) begin
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$display("Invalid instruction at PC=0x%h", r_id_pc);
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$display("%0t:\tInvalid instruction at PC=0x%h", $time, r_id_pc);
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s_id_halt = 1'b1;
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s_id_aluop = 3'hx;
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s_id_alu_seed = 1'bx;
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@ -236,12 +288,16 @@ reg [31:0] s_ex_ra;
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always @(*) begin
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s_ex_halt = 0;
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// NOTE: s_ex_data* exist for adding data paths bypassing regfile in the future
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s_ex_data1 = r_ex_s1;
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s_ex_data2 = r_ex_s2;
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case (r_ex_aluop)
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ALUOP_ADD: begin // seed=1: subtract
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s_ex_alu_out = s_ex_data1 + (s_ex_data2 ^ {32{r_ex_alu_seed}}) + r_ex_alu_seed;
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ALUOP_ADD: begin
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s_ex_alu_out = s_ex_data1 + s_ex_data2;
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end
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ALUOP_SUB: begin
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s_ex_alu_out = s_ex_data1 - s_ex_data2;
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end
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ALUOP_XOR: begin
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s_ex_alu_out = s_ex_data1 ^ s_ex_data2;
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@ -255,11 +311,11 @@ always @(*) begin
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ALUOP_SL: begin
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s_ex_alu_out = s_ex_data1 << s_ex_data2;
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end
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ALUOP_SR: begin // seed=1: arithmetic
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ALUOP_SRL: begin
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s_ex_alu_out = s_ex_data1 >> s_ex_data2;
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if (r_ex_alu_seed) begin
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s_ex_alu_out = s_ex_data1 >>> s_ex_data2;
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end
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end
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ALUOP_SRA: begin
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s_ex_alu_out = s_ex_data1 >>> s_ex_data2;
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end
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ALUOP_SLT: begin
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s_ex_alu_out = $signed(s_ex_data1) < $signed(s_ex_data2);
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@ -285,19 +341,19 @@ always @(*) begin
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s_mem_halt = 0;
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s_mem_bp = 0;
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if (r_mem_store) begin
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mem_data_en = 1;
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mem_data_we = 1;
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s_mem_bp = !mem_data_done;
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end else if (r_mem_load) begin
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mem_data_en = 1;
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mem_data_we = 0;
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s_mem_bp = !mem_data_valid;
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end else begin
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mem_data_en = 0;
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mem_data_we = 0;
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s_mem_bp = 0;
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end
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// if (r_mem_store) begin
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// mem_data_en = 1;
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// mem_data_we = 1;
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// s_mem_bp = !mem_data_done;
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// end else if (r_mem_load) begin
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// mem_data_en = 1;
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// mem_data_we = 0;
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// s_mem_bp = !mem_data_valid;
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// end else begin
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// mem_data_en = 0;
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// mem_data_we = 0;
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// s_mem_bp = 0;
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// end
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end
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// WB
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