trying to get sim to run in CI properly

.github/workflows/build.yml

@@ -29,6 +29,19 @@ jobs:
             -c "\
             riscv64-unknown-elf-gcc --version && \
             cd tests/test_basic && \
-            riscv64-unknown-elf-as -march=rv32i -mabi=ilp32 test.S -o test.o && \
+            riscv64-unknown-elf-as test.S -o test.o && \
+            riscv64-unknown-elf-ld -T tb.ld test.o -o test.elf && \
+            riscv64-unknown-elf-objcopy --target=verilog test.elf test.hex && \
             echo "done" \
             "
+
+      - name: Run Simulation
+        uses: docker://andrsmllr/iverilog:latest
+        with:
+          entrypoint: bash
+          args: |
+            -c "\
+            cd tests/test_basic && \
+            iverilog -g2012 -o test.out tb.sv ../../src/*.v -Y .sv -I ../../lib && \
+            ./test.out | tee test.log
+            "