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fix the code issues I just introduced

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This commit is contained in:
Brendan Haines 2021-07-02 02:39:43 -06:00
parent 0a9b182ef7
commit 17a95b58c8
1 changed files with 1 additions and 1 deletions
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2
hdl/tb/core_tb.v
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@ -72,7 +72,7 @@ always #2 clk = !clk;
core dut(
.clk(clk),
.reset(reset)
.reset(reset),
.mem_inst_addr(mem_inst_addr),
.mem_inst_data(mem_inst_data),