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BAD CODE: testing that CI pipeline catches verilog issues

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This commit is contained in:
Brendan Haines 2021-07-02 02:39:13 -06:00
parent 07c2fb570c
commit 0a9b182ef7
2 changed files with 2 additions and 2 deletions
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2
hdl/tb/core_tb.v
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@ -72,7 +72,7 @@ always #2 clk = !clk;
core dut(
.clk(clk),
.reset(reset),
.reset(reset)
.mem_inst_addr(mem_inst_addr),
.mem_inst_data(mem_inst_data),

2
test/test.S
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@ -9,7 +9,7 @@ _start:
lui x1, 0xfedcb # x1 = 0xfedcb000
# addi
addi x1, fx1, 0x789 # x1 = 0xfedcb789
addi x1, x1, 0x789 # x1 = 0xfedcb789
addi x2, x0, -1 # x2 = 0xffffffff
addi x3, x1, -0x777 # x3 = 0xfedcb012