From 0a9b182ef7e27f63f1f21d4a8115b3c05888c3d6 Mon Sep 17 00:00:00 2001
From: Brendan Haines <brendan.haines@gmail.com>
Date: Fri, 2 Jul 2021 02:39:13 -0600
Subject: [PATCH] BAD CODE: testing that CI pipeline catches verilog issues

---
 hdl/tb/core_tb.v | 2 +-
 test/test.S      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hdl/tb/core_tb.v b/hdl/tb/core_tb.v
index 1000770..45588bb 100644
--- a/hdl/tb/core_tb.v
+++ b/hdl/tb/core_tb.v
@@ -72,7 +72,7 @@ always #2 clk  = !clk;
 
 core dut(
     .clk(clk),
-    .reset(reset),
+    .reset(reset)
 
     .mem_inst_addr(mem_inst_addr),
     .mem_inst_data(mem_inst_data),
diff --git a/test/test.S b/test/test.S
index 9a73f29..5583508 100644
--- a/test/test.S
+++ b/test/test.S
@@ -9,7 +9,7 @@ _start:
     lui     x1, 0xfedcb         # x1  = 0xfedcb000
 
     # addi
-    addi    x1, fx1, 0x789       # x1  = 0xfedcb789
+    addi    x1, x1, 0x789       # x1  = 0xfedcb789
     addi    x2, x0, -1          # x2  = 0xffffffff
     addi    x3, x1, -0x777      # x3  = 0xfedcb012