BAD CODE: testing that CI pipeline catches verilog issues

2021-07-02 02:39:13 -06:00
parent 07c2fb570c
commit 0a9b182ef7
2 changed files with 2 additions and 2 deletions
--- a/hdl/tb/core_tb.v
+++ b/hdl/tb/core_tb.v
@ -72,7 +72,7 @@ always #2 clk  = !clk;

 core dut(
    .clk(clk),
-    .reset(reset),
+    .reset(reset)

    .mem_inst_addr(mem_inst_addr),
    .mem_inst_data(mem_inst_data),