mirror of
https://gitlab.com/brendanhaines/cpu.git
synced 2024-11-09 21:14:57 -07:00
31 lines
542 B
Plaintext
31 lines
542 B
Plaintext
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x00000000, LENGTH = 2k
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RAM (rwx) : ORIGIN = 0x00000800, LENGTH = 2k
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/* FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 512 */
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}
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SECTIONS
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{
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.text :
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{
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/* . = ALIGN(4); */
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_text = .;
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*(.text*)
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*(.rodata*)
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_etext = .;
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/* . = ALIGN(4); */
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} > ROM
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.data :
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{
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/* . = ALIGN(4); */
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_data = .;
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*(.data*)
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_edata = .;
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/* . = ALIGN(4); */
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} > RAM /*AT> FLASH*/
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}
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