cpu/testbench/test_basic/Makefile

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all: verify
TESTBENCH_V = $(wildcard *tb.sv)
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
LOGS = $(TESTBENCH_V:.sv=.log)
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SOURCE_C = $(wildcard *.c)
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SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o))
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CC = riscv64-linux-gnu-gcc
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CFLAGS = -march=rv32i -mabi=ilp32
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CPPFLAGS =
AS = riscv64-linux-gnu-as
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ASFLAGS = -march=rv32i -mabi=ilp32
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LD = riscv64-linux-gnu-ld
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LDFLAGS = -melf32lriscv_ilp32
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# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
# $(info $$SOURCE_V is [${SOURCE_V}])
# $(info $$LOGS is [${LOGS}])
# $(info $$SOURCE_C is [${SOURCE_C}])
# $(info $$SOURCE_AS is [${SOURCE_AS}])
# $(info $$OBJ is [${OBJ}])
%.o: %.S
$(AS) $(ASFLAGS) $^ -o $@
%.o: %.c
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%.s: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -S $^ -o $@
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%.elf: %.ld $(OBJ)
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$(LD) $(LDFLAGS) -T $^ -o $@
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%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
%.out: %.sv $(SOURCE_V)
iverilog -o $@ $^
%.vcd %.log: %.out %.hex
./$< | tee $(patsubst %.out, %.log, $<)
verify: $(LOGS)
@echo "Checking log for \"ERROR:\"..."
@! grep "ERROR:" $^
@echo "Checking log for \"SUCCESS:\"..."
@grep "SUCCESS:" $^
clean:
rm -rf *.vcd *.log *.out *.hex
.SECONDARY: %.log %.vcd
.PHONY: all clean verify