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https://gitlab.com/brendanhaines/cpu.git
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26 lines
481 B
INI
26 lines
481 B
INI
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XILINX = /opt/Xilinx/14.7/ISE_DS/ISE/
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PROJECT = riscv_core
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TARGET_PART = xc6slx25-3-ftg256
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VSOURCE = hdl/core.v hdl/top.v
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# VHDSOURCE = hdl/*.vhd
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VTEST = hdl/tb/core_tb.v
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# VHDTEST = hdl/tb/*.vhd
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TB = core_tb
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# XILINX_PLATFORM = lin64
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TOPLEVEL = top
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CONSTRAINTS = pins.ucf
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# COMMON_OPTS =
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# XST_OPTS =
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# NGDBUILD_OPTS =
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MAP_OPTS = -mt 2 -ol high
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PAR_OPTS = -mt 4 -ol high
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# BITGEN_OPTS = -g Compress
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# TRACE_OPTS =
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# FUSE_OPTS =
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PROGRAMMER = xc3sprog
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XC3SPROG_CABLE = ftdi
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