2021-08-11 00:28:00 -06:00
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2021-05-03 22:47:58 -06:00
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# RISC-V CPU
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2021-09-09 00:54:41 -06:00
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Short Term To Do:
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* add stalls for memory access
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2021-09-09 00:56:45 -06:00
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* use AXI for memory access (depends on AXIL memory module for test)
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2021-09-09 00:54:41 -06:00
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* add tests for non-pipelined case
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* get C working (may depend on memory stalls)
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2021-05-03 22:47:58 -06:00
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Desired features:
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* 1- or 5-stage pipeline selectable via parameter
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* AXI-lite Master for both instruction and data memory
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2021-09-09 00:54:41 -06:00
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* 32, 64, (or 128?) bit word size
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* floating point
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2021-05-03 22:47:58 -06:00
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* multiplication
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* division
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* instruction and data caches
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2021-09-09 00:54:41 -06:00
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* JTAG debug probe
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