cpu/README.md

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![pipeline status](https://gitlab.com/brendanhaines/0039_cpu/badges/master/pipeline.svg)
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# RISC-V CPU
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Short Term To Do:
* add stalls for memory access
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* use AXI for memory access (depends on AXIL memory module for test)
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* add tests for non-pipelined case
* get C working (may depend on memory stalls)
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Desired features:
* 1- or 5-stage pipeline selectable via parameter
* AXI-lite Master for both instruction and data memory
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* 32, 64, (or 128?) bit word size
* floating point
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* multiplication
* division
* instruction and data caches
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* JTAG debug probe