cpu/lib/skidbuffer.sv

53 lines
1.4 KiB
Systemverilog
Raw Permalink Normal View History

2022-11-19 23:41:15 -07:00
module skidbuffer #(
parameter WIDTH = 1
)(
input logic clk,
input logic reset,
input logic [WIDTH-1:0] in,
input logic in_valid,
output logic in_ready,
output logic [WIDTH-1:0] out,
output logic out_valid,
input logic out_ready
);
2022-12-01 01:07:15 -07:00
logic buffer_filled = 0;
logic [WIDTH-1:0] buffer_val;
2022-11-19 23:41:15 -07:00
2022-12-01 01:07:15 -07:00
always_ff @(posedge clk) begin
if (reset) begin
buffer_filled <= 0;
end else begin
if (in_valid && in_ready) begin
// input always gets stored whether it needs to be or not
buffer_val <= in;
end
2022-11-19 23:41:15 -07:00
2022-12-01 01:07:15 -07:00
if (buffer_filled) begin
if ((out_valid && out_ready) && !(in_valid && in_ready)) begin
// out_valid = 1 since buffer is full
buffer_filled <= 0;
end
end else begin
if ((in_valid && in_ready) && !(out_valid && out_ready)) begin
// in_ready = 1 since buffer is empty
buffer_filled <= 1;
end
end
2022-11-19 23:41:15 -07:00
end
2022-12-01 01:07:15 -07:00
end
2022-11-19 23:41:15 -07:00
2022-12-01 01:07:15 -07:00
always_comb begin
2022-11-19 23:41:15 -07:00
if (buffer_filled) begin
2022-12-01 01:07:15 -07:00
in_ready = out_ready;
out_valid = 1;
out = buffer_val;
2022-11-19 23:41:15 -07:00
end else begin
2022-12-01 01:07:15 -07:00
in_ready = 1;
out_valid = in_valid;
out = in;
2022-11-19 23:41:15 -07:00
end
end
endmodule