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17 lines
251 B
Verilog
17 lines
251 B
Verilog
module counter #(
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parameter BITS = 8
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)(
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input clk,
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input reset,
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output reg [BITS-1:0] y
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);
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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y <= 0;
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end else begin
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y <= y + 1;
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end
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end
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endmodule |