mirror of
https://gitlab.com/brendanhaines/ice40.git
synced 2024-11-09 21:14:58 -07:00
37 lines
488 B
Verilog
37 lines
488 B
Verilog
// Author: Brendan Haines
|
|
// Date: 2021-07-02
|
|
|
|
`timescale 1ns/1ps
|
|
|
|
module tb();
|
|
|
|
reg clk, reset;
|
|
wire [7:0] led;
|
|
|
|
top top(
|
|
.clk(clk),
|
|
.n_reset(~reset),
|
|
.led(led)
|
|
);
|
|
|
|
always #5 clk = ~clk;
|
|
|
|
initial begin
|
|
$dumpfile("tb.vcd");
|
|
$dumpvars(0, tb);
|
|
|
|
clk = 0;
|
|
reset = 1;
|
|
|
|
#10
|
|
reset = 0;
|
|
|
|
#2560
|
|
// #2560
|
|
$display("----------");
|
|
$display("Finished simulation.");
|
|
$display("Simulation time:\t%d ns", $realtime);
|
|
$finish;
|
|
end
|
|
|
|
endmodule |