mirror of
https://gitlab.com/brendanhaines/ice40.git
synced 2024-12-25 10:27:15 -07:00
fix sim output location
This commit is contained in:
parent
d850556bb7
commit
4e68e34cbf
17
Makefile
17
Makefile
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@ -1,15 +1,17 @@
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PROJ = top
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PROJ = top
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PIN_DEF = pins.pcf
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DEVICE = hx8k
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DEVICE = hx8k
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PACKAGE = ct256
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PACKAGE = ct256
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BUILD_DIR = build
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BUILD_DIR = build
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PIN_DEF = constraints/pins.pcf
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SOURCE_V = $(wildcard hdl/*.v)
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SOURCE_V = $(wildcard hdl/*.v)
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TESTBENCH_V = $(wildcard hdl/tb/*.v)
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TESTBENCH_V = $(wildcard hdl/tb/*.v)
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all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
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all: $(BUILD_DIR) $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
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$(BUILD_DIR)/%.blif: hdl/%.v
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$(BUILD_DIR):
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mkdir -p $(BUILD_DIR)
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$(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR)
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yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
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yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
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# yosys -p 'synth_ice40 -top top -blif $@' $<
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# yosys -p 'synth_ice40 -top top -blif $@' $<
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@ -29,14 +31,11 @@ sudo-prog: $(PROJ).bin
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@echo 'Executing prog as root!!!'
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@echo 'Executing prog as root!!!'
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sudo iceprog $<
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sudo iceprog $<
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$(BUILD_DIR):
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$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
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mkdir $(BUILD_DIR)
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$(BUILD_DIR)/tb.out: $(BUILD_DIR) $(SOURCE_V) $(TESTBENCH_V)
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iverilog $^ -o $@
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iverilog $^ -o $@
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sim: $(BUILD_DIR)/tb.out
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sim: $(BUILD_DIR)/tb.out
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$(BUILD_DIR)/tb.out
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cd $(BUILD_DIR) && ./tb.out
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clean:
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clean:
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rm -rf $(BUILD_DIR)
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rm -rf $(BUILD_DIR)
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@ -1,36 +1,23 @@
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[*]
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Fri Jul 2 06:30:08 2021
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[*] Fri Jul 2 07:11:25 2021
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[*]
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[*]
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[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb.vcd"
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[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/build/tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 06:30:05 2021"
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[dumpfile_mtime] "Fri Jul 2 07:10:41 2021"
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[dumpfile_size] 29504
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[dumpfile_size] 14906
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[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw"
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[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw"
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[timestart] 0
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[timestart] 0
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[size] 1920 1052
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[size] 1920 1052
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[pos] -1 -1
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[pos] -29 -29
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*-19.000000 765000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-20.000000 739000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[sst_width] 223
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[treeopen] tb.top.
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[signals_width] 94
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[sst_width] 233
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[signals_width] 279
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[sst_expanded] 1
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[sst_expanded] 1
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[sst_vpaned_height] 656
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[sst_vpaned_height] 311
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@28
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@28
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tb.clk
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tb.clk
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tb.reset
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tb.reset
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@c08022
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@8023
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tb.led[7:0]
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tb.led[7:0]
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@28
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(0)tb.led[7:0]
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(1)tb.led[7:0]
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(2)tb.led[7:0]
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(3)tb.led[7:0]
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(4)tb.led[7:0]
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(5)tb.led[7:0]
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(6)tb.led[7:0]
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(7)tb.led[7:0]
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@1401200
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-group_end
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[pattern_trace] 1
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[pattern_trace] 1
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[pattern_trace] 0
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[pattern_trace] 0
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