add basic example
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36
hdl/tb/tb.gtkw
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36
hdl/tb/tb.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
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[*] Fri Jul 2 06:30:08 2021
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[*]
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[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb.vcd"
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[dumpfile_mtime] "Fri Jul 2 06:30:05 2021"
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[dumpfile_size] 29504
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[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw"
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[timestart] 0
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[size] 1920 1052
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[pos] -1 -1
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*-19.000000 765000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[treeopen] tb.top.
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[sst_width] 233
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[signals_width] 279
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[sst_expanded] 1
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[sst_vpaned_height] 656
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@28
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tb.clk
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tb.reset
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@c08022
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tb.led[7:0]
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@28
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(0)tb.led[7:0]
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(1)tb.led[7:0]
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(2)tb.led[7:0]
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(3)tb.led[7:0]
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(4)tb.led[7:0]
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(5)tb.led[7:0]
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(6)tb.led[7:0]
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(7)tb.led[7:0]
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@1401200
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-group_end
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[pattern_trace] 1
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[pattern_trace] 0
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37
hdl/tb/tb.v
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37
hdl/tb/tb.v
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@@ -0,0 +1,37 @@
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// Author: Brendan Haines
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// Date: 2021-07-02
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`timescale 1ns/1ps
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module tb();
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reg clk, reset;
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wire [7:0] led;
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top top(
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.clk(clk),
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.n_reset(~reset),
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.led(led)
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);
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always #5 clk = ~clk;
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initial begin
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$dumpfile("tb.vcd");
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$dumpvars(0, tb);
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clk = 0;
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reset = 1;
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#10
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reset = 0;
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#2560
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// #2560
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$display("----------");
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$display("Finished simulation.");
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$display("Simulation time:\t%d ns", $realtime);
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$finish;
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end
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endmodule
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