add basic example

This commit is contained in:
2021-07-02 00:35:20 -06:00
parent e46403131f
commit 30dac2760c
7 changed files with 162 additions and 0 deletions

36
hdl/tb/tb.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 06:30:08 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb.vcd"
[dumpfile_mtime] "Fri Jul 2 06:30:05 2021"
[dumpfile_size] 29504
[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw"
[timestart] 0
[size] 1920 1052
[pos] -1 -1
*-19.000000 765000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[treeopen] tb.top.
[sst_width] 233
[signals_width] 279
[sst_expanded] 1
[sst_vpaned_height] 656
@28
tb.clk
tb.reset
@c08022
tb.led[7:0]
@28
(0)tb.led[7:0]
(1)tb.led[7:0]
(2)tb.led[7:0]
(3)tb.led[7:0]
(4)tb.led[7:0]
(5)tb.led[7:0]
(6)tb.led[7:0]
(7)tb.led[7:0]
@1401200
-group_end
[pattern_trace] 1
[pattern_trace] 0

37
hdl/tb/tb.v Normal file
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// Author: Brendan Haines
// Date: 2021-07-02
`timescale 1ns/1ps
module tb();
reg clk, reset;
wire [7:0] led;
top top(
.clk(clk),
.n_reset(~reset),
.led(led)
);
always #5 clk = ~clk;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
clk = 0;
reset = 1;
#10
reset = 0;
#2560
// #2560
$display("----------");
$display("Finished simulation.");
$display("Simulation time:\t%d ns", $realtime);
$finish;
end
endmodule