ice40/hdl/counter.v

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2021-07-02 00:35:20 -06:00
module counter #(
parameter BITS = 8
)(
input clk,
input reset,
output reg [BITS-1:0] y
);
always @(posedge clk or posedge reset) begin
if (reset) begin
y <= 0;
end else begin
y <= y + 1;
end
end
endmodule