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Brendan Haines 449efd3c3c use systemverilog 2012 for simulation
2022-11-19 18:41:25 -07:00
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main.c rename testbench to tests 2021-09-09 00:58:28 -06:00
Makefile use systemverilog 2012 for simulation 2022-11-19 18:41:25 -07:00
README.md rename testbench to tests 2021-09-09 00:58:28 -06:00
tb.ld rename testbench to tests 2021-09-09 00:58:28 -06:00
tb.sv rename testbench to tests 2021-09-09 00:58:28 -06:00
test.S rename testbench to tests 2021-09-09 00:58:28 -06:00

README.md

basic_test

Verify basic usage of all instructions. Includes tests to ensure pipeline stalls sufficiently for correctness but does not test for unnecessary stalls.

Currently store/load does not implement proper stalling so these operations are padded with nop