mirror of
https://gitlab.com/brendanhaines/cpu.git
synced 2024-12-26 19:16:48 -07:00
65 lines
1.3 KiB
Makefile
65 lines
1.3 KiB
Makefile
all: verify
|
|
|
|
TESTBENCH_V = $(wildcard *tb.sv)
|
|
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
|
|
SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
|
|
LOGS = $(TESTBENCH_V:.sv=.log)
|
|
|
|
# SOURCE_C = $(wildcard *.c)
|
|
SOURCE_C =
|
|
SOURCE_AS = $(wildcard *.S)
|
|
OBJ = $(notdir $(SOURCE_AS:.S=.o))
|
|
OBJ += $(notdir $(SOURCE_C:.c=.o))
|
|
|
|
CC = riscv64-linux-gnu-gcc-8
|
|
# CFLAGS = -march=rv32i -mabi=ilp32
|
|
CFLAGS = -march=rv64i -mabi=lp64
|
|
|
|
CPPFLAGS =
|
|
|
|
AS = riscv64-linux-gnu-as
|
|
ASFLAGS = $(CFLAGS)
|
|
|
|
LD = riscv64-linux-gnu-ld
|
|
LDFLAGS = -T
|
|
|
|
|
|
# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
|
|
# $(info $$SOURCE_V is [${SOURCE_V}])
|
|
# $(info $$LOGS is [${LOGS}])
|
|
# $(info $$SOURCE_C is [${SOURCE_C}])
|
|
# $(info $$SOURCE_AS is [${SOURCE_AS}])
|
|
# $(info $$OBJ is [${OBJ}])
|
|
|
|
|
|
%.o: %.S
|
|
$(AS) $(ASFLAGS) $^ -o $@
|
|
|
|
%.o: %.c
|
|
$(CC) $(CPPFLAGS) $(CFLAGS) $^ -o $@
|
|
|
|
%.elf: %.ld $(OBJ)
|
|
$(LD) $(LDFLAGS) $^ -o $@
|
|
|
|
%.hex: %.elf
|
|
riscv64-linux-gnu-objcopy --target=verilog $< $@
|
|
|
|
%.out: %.sv $(SOURCE_V)
|
|
iverilog -o $@ $^
|
|
|
|
%.vcd %.log: %.out %.hex
|
|
./$< | tee $(patsubst %.out, %.log, $<)
|
|
|
|
verify: $(LOGS)
|
|
@echo "Checking log for \"ERROR:\"..."
|
|
@! grep "ERROR:" $^
|
|
@echo "Checking log for \"SUCCESS:\"..."
|
|
@grep "SUCCESS:" $^
|
|
|
|
clean:
|
|
rm -rf *.vcd *.log *.out *.hex
|
|
|
|
.SECONDARY: %.log %.vcd
|
|
.PHONY: all clean verify
|
|
|