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37 lines
1.1 KiB
Systemverilog
37 lines
1.1 KiB
Systemverilog
interface axi_lite();
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 12;
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// Global
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logic ACLK;
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logic ARESETn;
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// Write address
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logic AWVALID;
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logic [ADDR_WIDTH-1:0] AWADDR;
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logic [2:0] AWPROT;
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logic AWREADY;
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// Write data
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logic WVALID;
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logic [DATA_WIDTH-1:0] WDATA;
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logic [(DATA_WIDTH/8)-1:0] WSTRB;
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logic WREADY;
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// Write response
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logic BVALID;
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logic BREADY;
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logic [1:0] BRESP;
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// Read address
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logic ARVALID;
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logic [ADDR_WIDTH-1:0] ARADDR;
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logic [2:0] ARPROT;
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logic ARREADY;
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// Read data
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logic RVALID;
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logic [DATA_WIDTH-1:0] RDATA;
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logic [1:0] RRESP;
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logic RREADY;
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endinterface
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