cpu/testbench/test_basic/tb.ld

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542 B
Plaintext

OUTPUT_ARCH( "riscv" )
ENTRY(_start)
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 2k
RAM (rwx) : ORIGIN = 0x00000800, LENGTH = 2k
/* FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 512 */
}
SECTIONS
{
.text :
{
/* . = ALIGN(4); */
_text = .;
*(.text*)
*(.rodata*)
_etext = .;
/* . = ALIGN(4); */
} > ROM
.data :
{
/* . = ALIGN(4); */
_data = .;
*(.data*)
_edata = .;
/* . = ALIGN(4); */
} > RAM /*AT> FLASH*/
}