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https://gitlab.com/brendanhaines/cpu.git
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180 lines
9.9 KiB
Verilog
180 lines
9.9 KiB
Verilog
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// IEEE 1149.1 - digital
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// IEEE 1149.4 - analog / mixed-signal
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// IEEE 1149.5 - system level
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// IEEE 1149.6 - ac-coupled, differential nets
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// IEEE 1532 - boundary scan (superset of IEEE 1149.1)
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// References:
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// http://www.interfacebus.com/Design_Connector_JTAG_Bus.html
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// Designing to IEEE 1149.1-2013
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module jtag_tap(
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input wire jtag_tck,
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input wire jtag_tms, // tie high to disable module
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input wire jtag_tdi,
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output reg jtag_tdo,
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input wire jtag_trst, // [optional] async active low reset
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);
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// NOTE: do not connect jtag_trst to any system logic (only tie to test logic)
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// For instance a reset input to the IC must not change the JTAG TAP state
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// TODO: TMP controller (IEEE 1149.1-2013 6.2.1)
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// State values according to IEEE 1149.1-2013
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localparam STATE_EXIT_2_DR = 4'h0,
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STATE_EXIT_1_DR = 4'h1,
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STATE_SHIFT_DR = 4'h2,
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STATE_PAUSE_DR = 4'h3,
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STATE_SELECT_IR_SCAN = 4'h4,
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STATE_UPDATE_DR = 4'h5,
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STATE_CAPTURE_DR = 4'h6,
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STATE_SELECT_DR_SCAN = 4'h7,
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STATE_EXIT_2_IR = 4'h8,
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STATE_EXIT_1_IR = 4'h9,
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STATE_SHIFT_IR = 4'hA,
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STATE_PAUSE_IR = 4'hB,
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STATE_RUN_TEST_IDLE = 4'hC,
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STATE_UPDATE_IR = 4'hD,
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STATE_CAPTURE_IR = 4'hD,
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STATE_TEST_LOGIC_RESET = 4'hF;
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localparam INSTR_BYPASS = 8'hFF, // required always // may also be other codes: recommend 0
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INSTR_SAMPLE = 8'h, // required always
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INSTR_PRELOAD = 8'h, // required always
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INSTR_EXTEST = 8'h, // required always
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INSTR_IDCODE = 8'h, // required if IDCODE register is included
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INSTR_USERCODE = 8'h, // required if IDCODE register is included in a user-programmable component that does not allow programming via this test logic
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// INSTR_CLAMP = 8'hxx,
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// INSTR_HIGHZ = 8'hxx,
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INSTR_IC_RESET = 8'h, // required if reset selection register is included
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// INSTR_CLAMP_HOLD = 8'hxx, // required if TMP controller & TMP status register are included
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// INSTR_CLAMP_RELEASE = 8'hxx, // required if TMP controller & TMP status register are included
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// INSTR_TMP_STATUS = 8'hxx, // required if TMP controller & TMP status register are included
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// recommended if there is programmable I/O
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// INSTR_INIT_SETUP = 8'h, // required if initialization data register is included
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// INSTR_INIT_SETUP_CLAMP = 8'h, // required if initialization data register is included
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// INSTR_INIT_RUN = 8'h, // required if initialization status register is included
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// required registers
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reg [3:0] state = STATE_TEST_LOGIC_RESET;
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reg [7:0] reg_instruction_shift, reg_instruction;
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reg [7:0] reg_data;
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always @(posedge jtag_tck or posedge jtag_trst) begin : state_transitions
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if (jtag_trst == 1'b0) begin
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state <= STATE_TEST_LOGIC_RESET;
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end else begin
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case (state) begin
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STATE_TEST_LOGIC_RESET: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_RUN_TEST_IDLE;
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STATE_RUN_TEST_IDLE: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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STATE_SELECT_DR_SCAN: state <= jtag_tms ? STATE_SELECT_IR_SCAN : STATE_CAPTURE_DR;
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STATE_CAPTURE_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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STATE_SHIFT_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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STATE_EXIT_1_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_PAUSE_DR;
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STATE_PAUSE_DR: state <= jtag_tms ? STATE_EXIT_2_DR : STATE_PAUSE_DR;
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STATE_EXIT_2_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_SHIFT_DR;
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STATE_UPDATE_DR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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STATE_SELECT_IR_SCAN: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_CAPTURE_IR;
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STATE_CAPTURE_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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STATE_SHIFT_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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STATE_EXIT_1_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_PAUSE_IR;
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STATE_PAUSE_IR: state <= jtag_tms ? STATE_EXIT_2_IR : STATE_PAUSE_IR;
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STATE_EXIT_2_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_SHIFT_IR;
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STATE_UPDATE_IR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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end
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end
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end
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always @(posedge jtag_tck or posedge jtag_trst) begin : actions_posedge
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if (jtag_trst == 1'b0 || state == STATE_TEST_LOGIC_RESET) begin
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reg_instruction_shift <= 8'hxx;
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reg_instruction <= INSTR_IDCODE;
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end else begin
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case (state)
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STATE_TEST_LOGIC_RESET: begin
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reg_instruction_shift <= 8'hxx;
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reg_instruction <= INSTR_IDCODE;
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end
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STATE_CAPTURE_IR: begin
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// TODO: check MSB/LSB first
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reg_instruction_shift[1:0] <= 2'b01;
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reg_instruction_shift[7:2] <= 6'h00; // these bits may be chosen to be any fixed value
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// reg_instruction <= reg_instruction;
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end
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STATE_SHIFT_IR: begin
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// TODO: check MSB/LSB first
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reg_instruction_shift[7] <= jtag_tdi;
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reg_instruction_shift[6:0] <= reg_instruction_shift[7:1];
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// reg_instruction <= reg_instruction;
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end
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STATE_EXIT_1_IR,
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STATE_EXIT_2_IR,
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STATE_PAUSE_IR: begin
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// reg_instruction_shift <= reg_instruction_shift;
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// reg_instruction <= reg_instruction;
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end
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STATE_UPDATE_IR: begin
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// reg_instruction_shift <= reg_instruction_shift;
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reg_instruction <= reg_instruction_shift;
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// TODO: do this on negedge? see pg 70
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end
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default: begin
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reg_instruction_shift <= 8'hxx;
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// reg_instruction <= reg_instruction;
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end
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endcase
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// case (state) begin
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// STATE_TEST_LOGIC_RESET: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_RUN_TEST_IDLE;
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// STATE_RUN_TEST_IDLE: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// STATE_SELECT_DR_SCAN: state <= jtag_tms ? STATE_SELECT_IR_SCAN : STATE_CAPTURE_DR;
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// STATE_CAPTURE_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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// STATE_SHIFT_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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// STATE_EXIT_1_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_PAUSE_DR;
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// STATE_PAUSE_DR: state <= jtag_tms ? STATE_EXIT_2_DR : STATE_PAUSE_DR;
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// STATE_EXIT_2_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_SHIFT_DR;
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// STATE_UPDATE_DR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// STATE_SELECT_IR_SCAN: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_CAPTURE_IR;
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// STATE_CAPTURE_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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// STATE_SHIFT_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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// STATE_EXIT_1_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_PAUSE_IR;
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// STATE_PAUSE_IR: state <= jtag_tms ? STATE_EXIT_2_IR : STATE_PAUSE_IR;
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// STATE_EXIT_2_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_SHIFT_IR;
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// STATE_UPDATE_IR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// end
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end
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end
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always @(negedge jtag_tck or posedge jtag_trst) begin : actions_negedge
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if (jtag_trst == 1'b0 || state == STATE_TEST_LOGIC_RESET) begin
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end else begin
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// case (state) begin
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// STATE_TEST_LOGIC_RESET: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_RUN_TEST_IDLE;
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// STATE_RUN_TEST_IDLE: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// STATE_SELECT_DR_SCAN: state <= jtag_tms ? STATE_SELECT_IR_SCAN : STATE_CAPTURE_DR;
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// STATE_CAPTURE_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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// STATE_SHIFT_DR: state <= jtag_tms ? STATE_EXIT_1_DR : STATE_SHIFT_DR;
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// STATE_EXIT_1_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_PAUSE_DR;
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// STATE_PAUSE_DR: state <= jtag_tms ? STATE_EXIT_2_DR : STATE_PAUSE_DR;
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// STATE_EXIT_2_DR: state <= jtag_tms ? STATE_UPDATE_DR : STATE_SHIFT_DR;
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// STATE_UPDATE_DR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// STATE_SELECT_IR_SCAN: state <= jtag_tms ? STATE_TEST_LOGIC_RESET : STATE_CAPTURE_IR;
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// STATE_CAPTURE_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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// STATE_SHIFT_IR: state <= jtag_tms ? STATE_EXIT_1_IR : STATE_SHIFT_IR;
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// STATE_EXIT_1_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_PAUSE_IR;
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// STATE_PAUSE_IR: state <= jtag_tms ? STATE_EXIT_2_IR : STATE_PAUSE_IR;
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// STATE_EXIT_2_IR: state <= jtag_tms ? STATE_UPDATE_IR : STATE_SHIFT_IR;
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// STATE_UPDATE_IR: state <= jtag_tms ? STATE_SELECT_DR_SCAN : STATE_RUN_TEST_IDLE;
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// end
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end
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end
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endmodule
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