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cpu
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449efd3c3cd7d964ffd3665a0adf90013e4808a9
cpu
/
tests
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Brendan Haines
449efd3c3c
use systemverilog 2012 for simulation
2022-11-19 18:41:25 -07:00
..
common
implement axi-lite to wishbone bridge. Untested
2022-11-19 18:37:35 -07:00
test_basic
use systemverilog 2012 for simulation
2022-11-19 18:41:25 -07:00
test_c
use systemverilog 2012 for simulation
2022-11-19 18:41:25 -07:00
.gitignore
rename testbench to tests
2021-09-09 00:58:28 -06:00
basic_test.gtkw
rename testbench to tests
2021-09-09 00:58:28 -06:00
Makefile
rename testbench to tests
2021-09-09 00:58:28 -06:00
