lib/axil_ata.sv

@@ -1,53 +0,0 @@
-module axil_ata(
-
-    ///// AXI4-Lite Slave /////
-
-    // Write address
-    input logic axil_awvalid,
-    output logic axil_awready,
-    input logic [ADDR_WIDTH-1:0] axil_awaddr,
-    input logic [2:0] axil_awprot,
-
-    // Write data
-    input logic axil_wvalid,
-    output logic axil_wready,
-    input logic [DATA_WIDTH-1:0] axil_wdata,
-    input logic [DATA_WIDTH/8 - 1:0] axil_wstrb,
-
-    // Write response
-    output logic axil_bvalid,
-    input logic axil_bready,
-    output logic [1:0] axil_bresp,
-
-    // Read address
-    input logic axil_arvalid,
-    output logic axil_arready,
-    input logic [ADDR_WIDTH-1:0] axil_araddr,
-    input logic [2:0] axil_arprot,
-
-    // Read data
-    output logic axil_rvalid,
-    input logic axil_rready,
-    output logic [DATA_WIDTH-1:0] axil_rdata,
-    output logic [1:0] axil_rresp,
-
-    ///// Parallel ATA Master /////
-    output  logic           ata_n_reset,            // reset
-    inout   wire    [15:0]  ata_data,               // data
-    output  logic           ata_n_diow,             // write strobe
-    output  logic           ata_n_dior,             // read strobe
-    input   wire            ata_iordy,              //
-    input   wire            ata_irq,                // interrupt request
-    output  logic   [2:0]   ata_addr,               // address
-    output  logic   [1:0]   ata_n_cs,               // chip select
-    input   wire            ata_activity,           // LED driver
-    xx      wire            ata_cable_select,       //
-    xx      wire            ata_dmarq,              // DMA request
-    xx      wire            ata_ddack,              // DMA acknowledge
-    xx      wire            ata_gpio_dma66_detect,  //
-    xx      wire            ata_n_iocs16            // IO ChipSelect 16
-);
-
-
-
-endmodule

lib/axil_wb_bridge.sv

@@ -7,7 +7,7 @@ module axil_wb_bridge #(
     input logic clk,
     input logic reset,
 
-    ///// AXI4-Lite Slave /////
+    ///// AXI4-Lite /////
 
     // Write address
     input logic axil_awvalid,

lib/skidbuffer.sv

@@ -1,4 +1,4 @@
-module axis_skidbuffer #(
+module skidbuffer #(
     parameter WIDTH = 1
 )(
     input logic clk,

lib/tb/axil_ata_tb.sv

@@ -1,21 +0,0 @@
-`include "bh_assert.sv"
-`timescale 1ns/1ps
-
-import bh_assert::bh_assert_equal;
-import bh_assert::bh_assert_stats;
-import bh_assert::bh_info;
-
-module axil_ata_tb();
-
-axil_ata dut();
-
-initial begin
-    $dumpfile("axil_ata_tb.vcd");
-    $dumpvars(0, axil_ata_tb);
-
-    #10
-    bh_assert_stats();
-    $finish;
-end
-
-endmodule

lib/tb/axil_wb_bridge_tb.sv

@@ -255,10 +255,6 @@ initial begin
     #10
     bh_assert_stats();
     $finish;
-
-
-    // TODO: add more exhaustive testing
-
 end
 
 endmodule

lib/tb/skidbuffer_tb.sv

@@ -4,7 +4,7 @@
 import bh_assert::bh_assert_equal;
 import bh_assert::bh_assert_stats;
 
-module axis_skidbuffer_tb();
+module skidbuffer_tb();
     parameter WIDTH = 15;
     parameter TEST_LIST_LENGTH = 256;
 
@@ -17,7 +17,7 @@ module axis_skidbuffer_tb();
     wire out_valid;
     logic out_ready = 0;
 
-    axis_skidbuffer #(
+    skidbuffer #(
         .WIDTH(WIDTH)
     ) dut (
         .clk(clk),
@@ -40,8 +40,8 @@ module axis_skidbuffer_tb();
     always #5 clk = !clk;
 
     initial begin
-        $dumpfile("axis_skidbuffer_tb.vcd");
+        $dumpfile("skidbuffer_tb.vcd");
-        $dumpvars(0, axis_skidbuffer_tb);
+        $dumpvars(0, skidbuffer_tb);
 
         for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
             in_list[i] = $urandom();
@@ -71,12 +71,10 @@ module axis_skidbuffer_tb();
         end
 
         if (reset == 0 && out_valid && out_ready) begin
-            if (out_count < TEST_LIST_LENGTH) begin
             bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
             out_count <= out_count + 1;
         end
     end
-    end
 
     wire [WIDTH-1:0] out_correct;
     assign out_correct = in_list[out_count];

tests/basic_test.gtkw

@@ -2,10 +2,10 @@
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
 [*] Wed Aug 11 06:10:48 2021
 [*]
-[dumpfile] "/home/brendan/Documents/projects/cpu/tests/test_basic/tb.vcd"
+[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/testbench/basic_test/tb.vcd"
 [dumpfile_mtime] "Wed Aug 11 06:09:59 2021"
 [dumpfile_size] 511500
-[savefile] "/home/brendan/Documents/projects/cpu/tests/basic_test.gtkw"
+[savefile] "/home/brendan/Documents/Projects/0039_cpu/testbench/testbench_tb.gtkw"
 [timestart] 0
 [size] 1920 1052
 [pos] -1970 -28