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synced 2024-12-25 10:36:49 -07:00
fix rdata output
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@ -78,9 +78,12 @@ logic [1:0] state_wb = STATE_IDLE;
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always_ff @(posedge clk) begin
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if (reset) begin
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waddr_valid <= 0;
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waddr_legal <= 1; // unnecessary
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wdata_valid <= 0;
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wdata_legal <= 1; // unnecessary
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w_complete <= 0;
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raddr_valid <= 0;
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raddr_legal <= 1; // unnecessary
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rdata_valid <= 0;
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state_wb <= STATE_IDLE;
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end else begin
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@ -191,6 +194,7 @@ always_comb begin
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// axil read data
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axil_rvalid = rdata_valid;
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axil_rdata = rdata;
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axil_rresp = raddr_legal ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR;
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// wishbone
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@ -146,6 +146,8 @@ initial begin
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bh_assert_equal(axil_bvalid, 0, "Initial bvalid");
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bh_assert_equal(axil_rvalid, 0, "Initial rvalid");
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// Write 0xdeadbeef @ 12
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#10
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bh_info("Starting write...");
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axil_awaddr = 12;
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@ -184,6 +186,8 @@ initial begin
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axil_bready = 0;
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bh_info("Write complete...");
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// Read 0x00000000 @ 13
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#10
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bh_info("Starting Read...");
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axil_araddr = 13;
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@ -215,6 +219,39 @@ initial begin
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axil_rready = 0;
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bh_info("Read complete...");
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// Read 0xdeadbeef @ 12
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#10
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bh_info("Starting Read...");
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axil_araddr = 12;
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axil_arprot = 0; // TODO: protection values
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axil_arvalid = 1;
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#10
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axil_arvalid = 0;
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#10
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bh_assert_equal(wb_stb_o, 1, "Wishbone read stb");
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bh_assert_equal(wb_sel_o, 1, "Wishbone read sel");
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bh_assert_equal(wb_cyc_o, 1, "Wishbone read cyc");
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bh_assert_equal(wb_we_o, 0, "Wishbone read we");
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wb_ack_i = 1;
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#10
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bh_assert_equal(wb_stb_o && wb_sel_o && wb_cyc_o, 0, "Wishbone read complete (stb && sel && cyc)");
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wb_ack_i = 0;
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#10
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bh_assert_equal(axil_rvalid, 1, "Read rvalid");
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bh_assert_equal(axil_rdata, 32'hdeadbeef, "Read rdata");
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bh_assert_equal(axil_rresp, 0, "Read rresp");
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axil_rready = 1;
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#10
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bh_assert_equal(axil_rvalid, 0, "Read rvalid");
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axil_rready = 0;
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bh_info("Read complete...");
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#10
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bh_assert_stats();
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$finish;
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