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fix rdata output

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Brendan Haines 2022-12-07 20:03:13 -07:00
parent 2c19633fb5
commit f8c7460b29
2 changed files with 41 additions and 0 deletions
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4
lib/axil_wb_bridge.sv
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@ -78,9 +78,12 @@ logic [1:0] state_wb = STATE_IDLE;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) begin if (reset) begin
waddr_valid <= 0; waddr_valid <= 0;
waddr_legal <= 1; // unnecessary
wdata_valid <= 0; wdata_valid <= 0;
wdata_legal <= 1; // unnecessary
w_complete <= 0; w_complete <= 0;
raddr_valid <= 0; raddr_valid <= 0;
raddr_legal <= 1; // unnecessary
rdata_valid <= 0; rdata_valid <= 0;
state_wb <= STATE_IDLE; state_wb <= STATE_IDLE;
end else begin end else begin
@ -191,6 +194,7 @@ always_comb begin
// axil read data // axil read data
axil_rvalid = rdata_valid; axil_rvalid = rdata_valid;
axil_rdata = rdata;
axil_rresp = raddr_legal ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR; axil_rresp = raddr_legal ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR;
// wishbone // wishbone

37
lib/tb/axil_wb_bridge_tb.sv
View File

@ -146,6 +146,8 @@ initial begin
bh_assert_equal(axil_bvalid, 0, "Initial bvalid"); bh_assert_equal(axil_bvalid, 0, "Initial bvalid");
bh_assert_equal(axil_rvalid, 0, "Initial rvalid"); bh_assert_equal(axil_rvalid, 0, "Initial rvalid");
// Write 0xdeadbeef @ 12
#10 #10
bh_info("Starting write..."); bh_info("Starting write...");
axil_awaddr = 12; axil_awaddr = 12;
@ -184,6 +186,8 @@ initial begin
axil_bready = 0; axil_bready = 0;
bh_info("Write complete..."); bh_info("Write complete...");
// Read 0x00000000 @ 13
#10 #10
bh_info("Starting Read..."); bh_info("Starting Read...");
axil_araddr = 13; axil_araddr = 13;
@ -215,6 +219,39 @@ initial begin
axil_rready = 0; axil_rready = 0;
bh_info("Read complete..."); bh_info("Read complete...");
// Read 0xdeadbeef @ 12
#10
bh_info("Starting Read...");
axil_araddr = 12;
axil_arprot = 0; // TODO: protection values
axil_arvalid = 1;
#10
axil_arvalid = 0;
#10
bh_assert_equal(wb_stb_o, 1, "Wishbone read stb");
bh_assert_equal(wb_sel_o, 1, "Wishbone read sel");
bh_assert_equal(wb_cyc_o, 1, "Wishbone read cyc");
bh_assert_equal(wb_we_o, 0, "Wishbone read we");
wb_ack_i = 1;
#10
bh_assert_equal(wb_stb_o && wb_sel_o && wb_cyc_o, 0, "Wishbone read complete (stb && sel && cyc)");
wb_ack_i = 0;
#10
bh_assert_equal(axil_rvalid, 1, "Read rvalid");
bh_assert_equal(axil_rdata, 32'hdeadbeef, "Read rdata");
bh_assert_equal(axil_rresp, 0, "Read rresp");
axil_rready = 1;
#10
bh_assert_equal(axil_rvalid, 0, "Read rvalid");
axil_rready = 0;
bh_info("Read complete...");
#10 #10
bh_assert_stats(); bh_assert_stats();
$finish; $finish;