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fix rdata output

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Brendan Haines 2022-12-07 20:03:13 -07:00
parent 2c19633fb5
commit f8c7460b29
2 changed files with 41 additions and 0 deletions
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4
lib/axil_wb_bridge.sv
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@ -78,9 +78,12 @@ logic [1:0] state_wb = STATE_IDLE;
always_ff @(posedge clk) begin
if (reset) begin
waddr_valid <= 0;
waddr_legal <= 1; // unnecessary
wdata_valid <= 0;
wdata_legal <= 1; // unnecessary
w_complete <= 0;
raddr_valid <= 0;
raddr_legal <= 1; // unnecessary
rdata_valid <= 0;
state_wb <= STATE_IDLE;
end else begin
@ -191,6 +194,7 @@ always_comb begin
// axil read data
axil_rvalid = rdata_valid;
axil_rdata = rdata;
axil_rresp = raddr_legal ? AXIL_RESP_OKAY : AXIL_RESP_SLVERR;
// wishbone