build test code into build directory
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19
hdl/Makefile
19
hdl/Makefile
@@ -1,19 +0,0 @@
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# SOURCE_V = $(wildcard *.v)
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# TESTBENCH_V = $(wildcard tb/*.v)
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SOURCE_V = core.v
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TESTBENCH_V = tb/core_tb.v
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all: sim
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tb.out: $(SOURCE_V) $(TESTBENCH_V)
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iverilog $^ -o $@
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sim: tb.out
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./tb.out
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clean:
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rm -rf tb.out tb.vcd
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.SECONDARY:
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.PHONY: all clean sim
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