add ability to wait for memory writes

hdl/core.v

@@ -6,12 +6,14 @@ module core(
     output reg [31:0] mem_inst_addr,
     input [31:0] mem_inst_data,
 
-    // // Memory - data
+    // Memory - data
     output reg [31:0] mem_data_addr,
     input [31:0] mem_data_rdata,
     output reg [31:0] mem_data_wdata,
     output reg [(32/8)-1:0] mem_data_wmask,
     output reg mem_data_we,
+    input mem_data_rvalid,
+    input mem_data_wready,
 
     // output reg [31:0] mem_data_waddr,
     // output reg [31:0] mem_data_wdata,
@@ -400,11 +402,18 @@ always @(*) begin
     s_mem_stall = 0;    // TODO: add stall logic when actually reading/writing
     s_mem_bp = 0;
 
+
     mem_data_addr = r_mem_alu_out;
     mem_data_wdata = regfile[r_mem_rs2];
     mem_data_wmask = 4'b1111;   // TODO: implement smaller writes
     mem_data_we = r_mem_store && r_mem_valid;
+    if (r_mem_store) begin
+        s_mem_stall = ~mem_data_wready;
+    end
     s_mem_load_data = mem_data_rdata;   // TODO: implement smaller reads
+    if (r_mem_load) begin
+        s_mem_stall = ~mem_data_rvalid;
+    end
 end
 
 // WB

hdl/tb/core_tb.gtkw

@@ -1,15 +1,15 @@
 [*]
-[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Fri Jul  2 10:38:55 2021
+[*] Sun Jul  4 01:38:44 2021
 [*]
 [dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
-[dumpfile_mtime] "Fri Jul  2 10:38:48 2021"
+[dumpfile_mtime] "Sun Jul  4 01:37:31 2021"
-[dumpfile_size] 685027
+[dumpfile_size] 682120
 [savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
-[timestart] 703450
+[timestart] 737900
-[size] 1920 1052
+[size] 1920 1016
 [pos] -1 -1
-*-14.000000 748830 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-13.000000 774000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] core_tb.
 [treeopen] core_tb.dut.
 [sst_width] 289
@@ -26,9 +26,14 @@ core_tb.reset
 @22
 core_tb.mem_data_addr[31:0]
 core_tb.mem_data_rdata[31:0]
+@28
+core_tb.mem_data_rvalid
+@22
 core_tb.mem_data_wdata[31:0]
 @28
 core_tb.mem_data_we
+@29
+core_tb.mem_data_wready
 @22
 core_tb.mem_inst_addr[31:0]
 core_tb.mem_inst_data[31:0]
@@ -169,9 +174,7 @@ core_tb.dut.r_ex_rs2[4:0]
 core_tb.dut.r_ex_rd[4:0]
 @22
 core_tb.dut.r_ex_s1[31:0]
-@23
 core_tb.dut.r_ex_s2[31:0]
-@22
 core_tb.dut.r_ex_aluop[3:0]
 @28
 core_tb.dut.r_ex_jump

hdl/tb/core_tb.v

@@ -44,6 +44,8 @@ reg [31:0] mem_data_rdata;
 wire [31:0] mem_data_wdata;
 wire [3:0] mem_data_wmask;
 wire mem_data_we;
+reg mem_data_wready;
+wire mem_data_rvalid = 1'b1;
 
 always @(*) begin
     if (mem_data_addr < MEM_LENGTH - 3) begin
@@ -66,6 +68,8 @@ end
 
 always @(posedge clk) begin
     if (mem_data_we) begin
+        if (mem_data_wready) begin
+            mem_data_wready = 1'b0;
             if (mem_data_addr < MEM_LENGTH && mem_data_addr >= MEM_ROM_LENGTH) begin
                 if (mem_data_wmask[0]) begin
                     mem[mem_data_addr+0] <= mem_data_wdata[7:0];
@@ -82,6 +86,11 @@ always @(posedge clk) begin
             end else begin
                 // ignore illegal writes
             end
+        end else begin
+            mem_data_wready = 1'b1;
+        end
+    end else begin
+        mem_data_wready = 1'b0;
     end
 end
 
@@ -114,6 +123,8 @@ core dut(
     .mem_data_wdata(mem_data_wdata),
     .mem_data_wmask(mem_data_wmask),
     .mem_data_we(mem_data_we),
+    .mem_data_rvalid(mem_data_rvalid),
+    .mem_data_wready(mem_data_wready),
 
     // .mem_data_addr(mem_data_addr),
     // .mem_data_wdata(mem_data_wdata),