partially working with common address space. loading of .data section has been disabled

hdl/tb/core_tb.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Fri Jul  2 08:01:39 2021
+[*] Fri Jul  2 09:02:34 2021
 [*]
 [dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
-[dumpfile_mtime] "Fri Jul  2 07:58:09 2021"
+[dumpfile_mtime] "Fri Jul  2 09:00:37 2021"
-[dumpfile_size] 681929
+[dumpfile_size] 808881
 [savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
-[timestart] 0
+[timestart] 656100
 [size] 1920 1052
 [pos] -1 -1
-*-20.000000 461000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-16.000000 728100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] core_tb.
 [treeopen] core_tb.dut.
 [sst_width] 289
@@ -22,9 +22,22 @@
 core_tb.clk
 core_tb.reset
 @200
--DUT
+-
 @22
+core_tb.mem_data_addr[31:0]
+core_tb.mem_data_rdata[31:0]
+core_tb.mem_data_wdata[31:0]
+@28
+core_tb.mem_data_we
+@22
+core_tb.mem_inst_addr[31:0]
+core_tb.mem_inst_data[31:0]
+@200
+-
+-DUT
+@23
 core_tb.dut.\regfile[0][31:0]
+@22
 core_tb.dut.\regfile[1][31:0]
 core_tb.dut.\regfile[2][31:0]
 core_tb.dut.\regfile[3][31:0]
@@ -89,9 +102,7 @@ core_tb.dut.\regfile[24][31:0]
 core_tb.dut.\regfile[25][31:0]
 core_tb.dut.\regfile[26][31:0]
 core_tb.dut.\regfile[27][31:0]
-@23
 core_tb.dut.\regfile[28][31:0]
-@22
 core_tb.dut.\regfile[29][31:0]
 core_tb.dut.\regfile[30][31:0]
 core_tb.dut.\regfile[31][31:0]

hdl/tb/core_tb.v

@@ -14,10 +14,10 @@ end
 
 wire dummy_out;
 
-localparam  MEM_INST_LENGTH = 256;  // words
+localparam  MEM_ROM_LENGTH = 2048 >> 2;  // words
-localparam  MEM_DATA_LENGTH = 256;  // words
+localparam  MEM_LENGTH = MEM_ROM_LENGTH + 2048 >> 2;  // words
 
-localparam  MEM_DATA_BASE   = 32'h00100000;
+localparam  MEM_DATA_BASE   = 32'h00000800;
 
 localparam  INST_NOP        = 32'h00000013;  // nop
 localparam  DATA_DEFAULT    = 32'h00000000;
@@ -26,34 +26,34 @@ localparam  DATA_INVALID    = 32'hdeadbeef;
 reg clk, reset;
 
 // Instruction memory
-reg [31:0] mem_inst [0:MEM_INST_LENGTH-1];
+reg [31:0] mem [0:MEM_LENGTH-1];
 wire [31:0] mem_inst_addr;
 wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
-wire [31:0] mem_inst_data = mem_inst_idx < MEM_INST_LENGTH ? mem_inst[mem_inst_idx] : INST_NOP;
+wire [31:0] mem_inst_data = mem_inst_idx < MEM_LENGTH ? mem[mem_inst_idx] : INST_NOP;
 
-initial begin: mem_inst_init
+initial begin: mem_init
     integer i;
-    for (i=0; i<MEM_INST_LENGTH; i=i+1) begin
+    for (i=0; i<MEM_LENGTH; i=i+1) begin
-        mem_inst[i] = INST_NOP;
+        mem[i] = INST_NOP;
     end
-    $readmemh("text.hex", mem_inst);
+    $readmemh("text.hex", mem);
 end
 
 // Data memory
-reg [31:0] mem_data [0:MEM_DATA_LENGTH-1];
+// reg [31:0] mem_data [0:MEM_DATA_LENGTH-1];
 wire [31:0] mem_data_addr;
 reg [31:0] mem_data_rdata;
 wire [31:0] mem_data_wdata;
 wire [3:0] mem_data_wmask;
 wire mem_data_we;
 
-initial begin: mem_data_init
+// initial begin: mem_data_init
-    integer i;
+//     integer i;
-    for (i=0; i<MEM_DATA_LENGTH; i=i+1) begin
+//     for (i=0; i<MEM_DATA_LENGTH; i=i+1) begin
-        mem_data[i] = DATA_DEFAULT;
+//         mem_data[i] = DATA_DEFAULT;
-    end
+//     end
-    $readmemh("data.hex", mem_data);
+//     $readmemh("data.hex", mem_data);
-end
+// end
 
 initial begin
     #0
@@ -150,29 +150,29 @@ core dut(
 //     .WB_RREADY()
 // );
 
-wire [31:0] mem_data_idx = (mem_data_addr - MEM_DATA_BASE) >> 2;
+wire [31:0] mem_data_idx = (mem_data_addr) >> 2;
 always @(*) begin
-    if (mem_data_idx < MEM_DATA_LENGTH) begin
+    if (mem_data_idx < MEM_LENGTH) begin
-        mem_data_rdata = mem_data[mem_data_idx];
+        mem_data_rdata = mem[mem_data_idx];
     end else begin
         mem_data_rdata = DATA_INVALID;
     end
 end
 
 always @(posedge clk) begin
-    if (mem_data_idx < MEM_DATA_LENGTH) begin
+    if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
         if (mem_data_we) begin
             if (mem_data_wmask[0]) begin
-                mem_data[mem_data_idx][7:0] <= mem_data_wdata[7:0];
+                mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
             end
             if (mem_data_wmask[1]) begin
-                mem_data[mem_data_idx][15:8] <= mem_data_wdata[15:8];
+                mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
             end
             if (mem_data_wmask[2]) begin
-                mem_data[mem_data_idx][23:16] <= mem_data_wdata[23:16];
+                mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
             end
             if (mem_data_wmask[3]) begin
-                mem_data[mem_data_idx][31:24] <= mem_data_wdata[31:24];
+                mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
             end
         end
     end else begin

test/test.S

@@ -229,7 +229,7 @@ test10:
     nop
     nop
     nop
-    lw      x11, 0(x9)          # x11 = 0xfedcba98
+    lw      x11, 0(x9)          # x11 = 0xfedcba98  # TODO: do something with this
     nop
     nop
     nop

test/test.ld

@@ -2,8 +2,8 @@ ENTRY(_start)
 
 MEMORY
 {
-    ROM (rx)    : ORIGIN = 0x00000000, LENGTH = 1024
+    ROM (rx)    : ORIGIN = 0x00000000, LENGTH = 2k
-    RAM (rwx)   : ORIGIN = 0x00100000, LENGTH = 1024
+    RAM (rwx)   : ORIGIN = 0x00000800, LENGTH = 2k
     /* FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 512 */
 }