I think this properly stalls for all implemented instructions so I don't need nops
This commit is contained in:
110
hdl/core.v
110
hdl/core.v
@ -90,6 +90,8 @@ reg r_ex_store, r_mem_store;
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reg r_ex_load, r_mem_load;
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reg [31:0] r_mem_wdata, r_wb_wdata;
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reg r_id_valid=0, r_ex_valid=0, r_mem_valid=0, r_wb_valid=0;
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reg r_ex_branch_pol;
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reg r_ex_branch;
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// IF
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reg s_if_stall = 0;
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@ -97,9 +99,9 @@ reg [31:0] s_if_next_pc;
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reg [31:0] s_if_inst;
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always @(*) begin
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s_if_stall = s_id_stall || 0;
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s_if_stall = s_id_stall;
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if (r_ex_jump && r_ex_valid) begin
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if (s_ex_take_branch && r_ex_valid) begin
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s_if_next_pc = s_ex_alu_out;
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// s_if_stall = 1'b1;
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end else begin
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@ -123,6 +125,7 @@ reg [3:0] s_id_aluop;
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reg s_id_invalid;
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reg s_id_jump, s_id_branch;
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reg s_id_store, s_id_load;
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reg s_id_branch_pol;
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// RV32I / RV64I / RV32M
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localparam OP_LUI = 7'b0110111,
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@ -156,7 +159,6 @@ localparam ALUOP_ADD = 4'b0000,
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always @(*) begin
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s_id_stall = s_ex_stall || 0;
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s_id_invalid = 0;
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s_id_store = 0;
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s_id_load = 0;
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@ -174,38 +176,68 @@ always @(*) begin
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s_id_immed_btype = {{19{r_id_inst[31]}}, r_id_inst[31], r_id_inst[7], r_id_inst[30:25], r_id_inst[11:8], 1'b0};
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s_id_immed_jtype = {{11{r_id_inst[31]}}, r_id_inst[31], r_id_inst[19:12], r_id_inst[20], r_id_inst[30:21], 1'b0};
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// default values
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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s_id_jump = 0;
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s_id_branch = 0;
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s_id_branch_pol = 1'bx;
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case (s_id_opcode)
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OP_LUI: begin // LUI
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s_id_s1 = 32'h00000000;
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s_id_s2 = s_id_immed_utype;
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s_id_aluop = ALUOP_ADD;
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s_id_jump = 0;
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s_id_branch = 0;
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end
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OP_AUIPC: begin // AUIPC
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s_id_s1 = r_id_pc;
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s_id_s2 = s_id_immed_utype;
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s_id_aluop = ALUOP_ADD;
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s_id_jump = 0;
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s_id_branch = 0;
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end
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OP_JAL: begin // JAL
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s_id_s1 = r_id_pc;
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s_id_s2 = s_id_immed_jtype;
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s_id_aluop = ALUOP_ADD;
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s_id_jump = 1;
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s_id_branch = 0;
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end
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OP_JALR: begin // JALR
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = s_id_immed_itype;
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s_id_aluop = ALUOP_ADD;
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s_id_jump = 1;
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s_id_branch = 0;
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end
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// OP_BRANCH: begin
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// end
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OP_BRANCH: begin
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = regfile[s_id_rs2];
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s_id_branch = 1;
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case (s_id_funct3)
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3'b000: begin // BEQ
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s_id_aluop = ALUOP_SUB;
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s_id_branch_pol = 0;
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end
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3'b001: begin // BNE
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s_id_aluop = ALUOP_SUB;
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s_id_branch_pol = 1;
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end
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3'b100: begin // BLT
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s_id_aluop = ALUOP_SLT;
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s_id_branch_pol = 1;
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end
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3'b101: begin // BGE
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s_id_aluop = ALUOP_SLT;
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s_id_branch_pol = 0;
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end
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3'b110: begin // BLTU
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s_id_aluop = ALUOP_SLTU;
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s_id_branch_pol = 1;
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end
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3'b111: begin // BGEU
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s_id_aluop = ALUOP_SLTU;
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s_id_branch_pol = 0;
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end
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default: s_id_invalid = 1;
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endcase
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end
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// OP_LOAD: begin
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// end
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@ -215,8 +247,6 @@ always @(*) begin
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OP_IMM: begin
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = s_id_immed_itype;
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s_id_jump = 0;
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s_id_branch = 0;
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casex ({s_id_funct3, s_id_funct7})
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10'b000xxxxxxx: s_id_aluop = ALUOP_ADD; // ADDI
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10'b010xxxxxxx: s_id_aluop = ALUOP_SLT; // SLTI
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@ -227,18 +257,12 @@ always @(*) begin
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10'b001000000x: s_id_aluop = ALUOP_SL; // SLLI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
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10'b101000000x: s_id_aluop = ALUOP_SRL; // SRLI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
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10'b101010000x: s_id_aluop = ALUOP_SRA; // SRAI // NOTE: technically s_id_funct7[0] must be 0 however GCC allows shifts of up to 63b despite assembling for 32b. I can tolerate this deviation from ISA spec at essentially no cost
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default: begin
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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s_id_invalid = 1;
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end
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default: s_id_invalid = 1;
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endcase
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end
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OP_ALU: begin
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = regfile[s_id_rs2];
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s_id_jump = 0;
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s_id_branch = 0;
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case ({s_id_funct3, s_id_funct7})
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10'b0000000000: s_id_aluop = ALUOP_ADD; // ADD
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10'b0000100000: s_id_aluop = ALUOP_SUB; // SUB
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@ -250,11 +274,7 @@ always @(*) begin
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10'b1110000000: s_id_aluop = ALUOP_AND; // AND
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10'b1010000000: s_id_aluop = ALUOP_SRL; // SRL
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10'b1010100000: s_id_aluop = ALUOP_SRA; // SRA
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default: begin
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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s_id_invalid = 1;
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end
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default: s_id_invalid = 1;
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endcase
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end
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// OP_FENCE: begin
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@ -264,14 +284,21 @@ always @(*) begin
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// end
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default: begin
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s_id_jump = 0;
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s_id_branch = 0;
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s_id_s1 = 32'hxxxxxxxx;
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s_id_s2 = 32'hxxxxxxxx;
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s_id_invalid = 1;
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end
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endcase
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s_id_stall = s_ex_stall ||
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(r_ex_valid &&
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(((r_ex_rd == s_id_rs1) && (s_id_rs1 != 0)) ||
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((r_ex_rd == s_id_rs2) && (s_id_rs2 != 0)))) ||
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(r_mem_valid &&
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(((r_mem_rd == s_id_rs1) && (s_id_rs1 != 0)) ||
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((r_mem_rd == s_id_rs2) && (s_id_rs2 != 0)))) ||
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(r_wb_valid &&
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(((r_wb_rd == s_id_rs1) && (s_id_rs1 != 0)) ||
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((r_wb_rd == s_id_rs2) && (s_id_rs2 != 0))));
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if (s_id_invalid) begin
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$display("%0t:\tInvalid instruction at PC=0x%h", $time, r_id_pc);
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s_id_aluop = 3'hx;
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@ -279,15 +306,16 @@ always @(*) begin
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end
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// EX
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reg s_ex_stall;
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reg s_ex_stall = 0;
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reg [31:0] s_ex_data1, s_ex_data2;
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reg [31:0] s_ex_alu_out;
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reg s_ex_alu_zero;
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reg [31:0] s_ex_ra;
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reg [31:0] s_ex_wdata;
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reg s_ex_take_branch;
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always @(*) begin
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s_ex_stall = s_mem_stall || 0;
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s_ex_stall = s_mem_stall;
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// NOTE: s_ex_data* exist for adding data paths bypassing regfile in the future
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s_ex_data1 = r_ex_s1;
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@ -331,6 +359,9 @@ always @(*) begin
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s_ex_alu_zero = (s_ex_alu_out == 0);
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s_ex_ra = r_ex_pc + 4;
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// s_ex_branch_addr = r_ex_pc +
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// TODO: determine and go to branch address (pc+offset)
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s_ex_take_branch = r_ex_jump || (r_ex_branch && (s_ex_alu_zero ^ r_ex_branch_pol));
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if (r_ex_jump) begin
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s_ex_wdata = s_ex_ra;
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end else begin
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@ -339,11 +370,11 @@ always @(*) begin
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end
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// MEM
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reg s_mem_stall;
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reg s_mem_stall = 0;
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reg s_mem_bp;
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always @(*) begin
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s_mem_stall = s_wb_stall || 0;
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s_mem_stall = 0; // TODO: add stall logic when actually reading/writing
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s_mem_bp = 0;
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// if (r_mem_store) begin
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@ -362,12 +393,10 @@ always @(*) begin
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end
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// WB
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reg s_wb_stall;
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reg [31:0] s_wb_data;
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reg s_wb_write;
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always @(*) begin
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s_wb_stall = 1'b0;
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// load instructions do not use output of alu in wb
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s_wb_data = r_wb_wdata;
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@ -428,12 +457,11 @@ always @(posedge clk) begin: pipeline_update
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if (!s_id_stall) begin
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r_id_pc <= r_if_pc;
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r_id_inst <= s_if_inst;
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r_id_valid <= ~(r_ex_jump && r_ex_valid);
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r_id_valid <= ~(s_ex_take_branch && r_ex_valid);
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end
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// EX
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if (!s_ex_stall) begin
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// TODO: also stall EX if taking branch
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r_ex_pc <= r_id_pc;
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r_ex_inst <= r_id_inst;
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r_ex_rd <= s_id_rd;
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@ -441,9 +469,11 @@ always @(posedge clk) begin: pipeline_update
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r_ex_s2 <= s_id_s2;
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r_ex_aluop <= s_id_aluop;
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r_ex_jump <= s_id_jump;
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r_ex_branch <= s_id_branch;
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r_ex_store <= s_id_store;
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r_ex_load <= s_id_load;
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r_ex_valid <= r_id_valid && ~(r_ex_jump && r_ex_valid);
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r_ex_valid <= r_id_valid && ~(s_ex_take_branch && r_ex_valid) && ~(s_id_stall && r_id_valid);
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r_ex_branch_pol <= s_id_branch_pol;
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end
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@ -463,7 +493,7 @@ always @(posedge clk) begin: pipeline_update
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end
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// WB
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if (!s_wb_stall) begin
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if (1) begin
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r_wb_pc <= r_mem_pc;
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r_wb_inst <= r_mem_inst;
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r_wb_rd <= r_mem_rd;
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