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Brendan Haines 2021-05-04 04:47:58 +00:00
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# RISC-V CPU
Harvard architecture
Desired features:
* 1- or 5-stage pipeline selectable via parameter
* AXI-lite Master for both instruction and data memory
* 32, 64, or 128 bit word size
* floating point support
* multiplication
* division
* instruction and data caches