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https://gitlab.com/brendanhaines/cpu.git
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ignore overrun at end of skidbuffer test
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parent
3b476cfc32
commit
71bc903f14
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@ -1,4 +1,4 @@
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module skidbuffer #(
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module axis_skidbuffer #(
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parameter WIDTH = 1
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parameter WIDTH = 1
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)(
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)(
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input logic clk,
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input logic clk,
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@ -4,7 +4,7 @@
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import bh_assert::bh_assert_equal;
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import bh_assert::bh_assert_equal;
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import bh_assert::bh_assert_stats;
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import bh_assert::bh_assert_stats;
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module skidbuffer_tb();
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module axis_skidbuffer_tb();
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parameter WIDTH = 15;
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parameter WIDTH = 15;
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parameter TEST_LIST_LENGTH = 256;
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parameter TEST_LIST_LENGTH = 256;
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@ -17,7 +17,7 @@ module skidbuffer_tb();
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wire out_valid;
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wire out_valid;
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logic out_ready = 0;
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logic out_ready = 0;
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skidbuffer #(
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axis_skidbuffer #(
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.WIDTH(WIDTH)
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.WIDTH(WIDTH)
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) dut (
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) dut (
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.clk(clk),
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.clk(clk),
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@ -40,8 +40,8 @@ module skidbuffer_tb();
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always #5 clk = !clk;
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always #5 clk = !clk;
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initial begin
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initial begin
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$dumpfile("skidbuffer_tb.vcd");
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$dumpfile("axis_skidbuffer_tb.vcd");
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$dumpvars(0, skidbuffer_tb);
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$dumpvars(0, axis_skidbuffer_tb);
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for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
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for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
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in_list[i] = $urandom();
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in_list[i] = $urandom();
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@ -71,10 +71,12 @@ module skidbuffer_tb();
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end
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end
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if (reset == 0 && out_valid && out_ready) begin
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if (reset == 0 && out_valid && out_ready) begin
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if (out_count < TEST_LIST_LENGTH) begin
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bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
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bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
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out_count <= out_count + 1;
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out_count <= out_count + 1;
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end
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end
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end
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end
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end
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wire [WIDTH-1:0] out_correct;
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wire [WIDTH-1:0] out_correct;
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assign out_correct = in_list[out_count];
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assign out_correct = in_list[out_count];
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