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passes quick test: beq, blt, bltu

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Brendan Haines
2020-11-09 20:01:25 -07:00
parent 06d0e07c61
commit 6e0d9c96a1
3 changed files with 100 additions and 35 deletions
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27
hdl/core.v
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@ -91,7 +91,8 @@ reg r_ex_load, r_mem_load;
reg [31:0] r_mem_wdata, r_wb_wdata;
reg r_id_valid=0, r_ex_valid=0, r_mem_valid=0, r_wb_valid=0;
reg r_ex_branch_pol;
reg r_ex_branch;
reg r_ex_branch, r_mem_branch, r_wb_branch;
reg [31:0] r_ex_immed_btype;
// IF
reg s_if_stall = 0;
@ -101,12 +102,10 @@ reg [31:0] s_if_inst;
always @(*) begin
s_if_stall = s_id_stall;
if (s_ex_take_branch && r_ex_valid) begin
s_if_next_pc = s_ex_alu_out;
// s_if_stall = 1'b1;
if (s_ex_take_branch) begin
s_if_next_pc = s_ex_branch_addr;
end else begin
s_if_next_pc = r_if_pc + 4;
// s_if_stall = 1'b0;
end
mem_inst_addr = r_if_pc;
@ -289,7 +288,7 @@ always @(*) begin
endcase
s_id_stall = s_ex_stall ||
(r_ex_valid &&
(r_ex_valid && (s_ex_take_branch == 0) &&
(((r_ex_rd == s_id_rs1) && (s_id_rs1 != 0)) ||
((r_ex_rd == s_id_rs2) && (s_id_rs2 != 0)))) ||
(r_mem_valid &&
@ -310,9 +309,9 @@ reg s_ex_stall = 0;
reg [31:0] s_ex_data1, s_ex_data2;
reg [31:0] s_ex_alu_out;
reg s_ex_alu_zero;
reg [31:0] s_ex_ra;
reg [31:0] s_ex_wdata;
reg s_ex_take_branch;
reg [31:0] s_ex_branch_addr;
always @(*) begin
s_ex_stall = s_mem_stall;
@ -358,14 +357,13 @@ always @(*) begin
endcase
s_ex_alu_zero = (s_ex_alu_out == 0);
s_ex_ra = r_ex_pc + 4;
// s_ex_branch_addr = r_ex_pc +
// TODO: determine and go to branch address (pc+offset)
s_ex_take_branch = r_ex_jump || (r_ex_branch && (s_ex_alu_zero ^ r_ex_branch_pol));
s_ex_take_branch = r_ex_valid && (r_ex_jump || (r_ex_branch && (s_ex_alu_zero ^ r_ex_branch_pol)));
if (r_ex_jump) begin
s_ex_wdata = s_ex_ra;
s_ex_wdata = r_ex_pc + 4;
s_ex_branch_addr = s_ex_alu_out;
end else begin
s_ex_wdata = s_ex_alu_out;
s_ex_branch_addr = r_ex_pc + r_ex_immed_btype;
end
end
@ -402,7 +400,7 @@ always @(*) begin
s_wb_data = r_wb_wdata;
// FIXME: always writes!!!
s_wb_write = 1; //!s_wb_stall;
s_wb_write = (r_wb_branch == 0);
end
// SYS
@ -474,6 +472,7 @@ always @(posedge clk) begin: pipeline_update
r_ex_load <= s_id_load;
r_ex_valid <= r_id_valid && ~(s_ex_take_branch && r_ex_valid) && ~(s_id_stall && r_id_valid);
r_ex_branch_pol <= s_id_branch_pol;
r_ex_immed_btype <= s_id_immed_btype;
end
@ -490,6 +489,7 @@ always @(posedge clk) begin: pipeline_update
r_mem_load <= r_ex_load;
r_mem_wdata <= s_ex_wdata;
r_mem_valid <= r_ex_valid;
r_mem_branch <= r_ex_branch;
end
// WB
@ -500,6 +500,7 @@ always @(posedge clk) begin: pipeline_update
r_wb_alu_out <= r_mem_alu_out;
r_wb_wdata <= r_mem_wdata;
r_wb_valid <= r_mem_valid;
r_wb_branch <= r_mem_branch;
end
// Register File