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change gcc prefix to match docker image

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Brendan Haines 2025-08-25 21:32:36 -06:00
parent 70a53c200c
commit 5eb65bce9d
2 changed files with 8 additions and 8 deletions
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8
tests/test_basic/Makefile
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@ -11,15 +11,15 @@ OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o)) OBJ += $(notdir $(SOURCE_C:.c=.o))
# Software compilation # Software compilation
CC = riscv64-linux-gnu-gcc CC = riscv64-unknown-elf-gcc
CFLAGS = -march=rv32i -mabi=ilp32 CFLAGS = -march=rv32i -mabi=ilp32
CPPFLAGS = CPPFLAGS =
AS = riscv64-linux-gnu-as AS = riscv64-unknown-elf-as
ASFLAGS = -march=rv32i -mabi=ilp32 ASFLAGS = -march=rv32i -mabi=ilp32
LD = riscv64-linux-gnu-ld LD = riscv64-unknown-elf-ld
LDFLAGS = -melf32lriscv_ilp32 LDFLAGS = -melf32lriscv_ilp32
# $(info $$TESTBENCH_V is [${TESTBENCH_V}]) # $(info $$TESTBENCH_V is [${TESTBENCH_V}])
@ -40,7 +40,7 @@ LDFLAGS = -melf32lriscv_ilp32
$(LD) $(LDFLAGS) -T $^ -o $@ $(LD) $(LDFLAGS) -T $^ -o $@
%.hex: %.elf %.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@ riscv64-unknown-elf-objcopy --target=verilog $< $@
# Hardware compilation # Hardware compilation
%.out: %.sv $(SOURCE_V) %.out: %.sv $(SOURCE_V)

8
tests/test_c/Makefile
View file

@ -10,18 +10,18 @@ SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o)) OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o)) OBJ += $(notdir $(SOURCE_C:.c=.o))
CC = riscv64-linux-gnu-gcc CC = riscv64-unknown-elf-gcc
CFLAGS = -march=rv32i -mabi=ilp32 CFLAGS = -march=rv32i -mabi=ilp32
# CFLAGS = -march=rv64i -mabi=lp64 # CFLAGS = -march=rv64i -mabi=lp64
# CFLAGS += -nostdlib -lgcc # CFLAGS += -nostdlib -lgcc
CPPFLAGS = CPPFLAGS =
AS = riscv64-linux-gnu-as AS = riscv64-unknown-elf-as
ASFLAGS = -march=rv32i -mabi=ilp32 ASFLAGS = -march=rv32i -mabi=ilp32
# ASFLAGS = -march=rv64i -mabi=lp64 # ASFLAGS = -march=rv64i -mabi=lp64
LD = riscv64-linux-gnu-ld LD = riscv64-unknown-elf-ld
LDFLAGS = -melf32lriscv_ilp32 LDFLAGS = -melf32lriscv_ilp32
# LDFLAGS = # LDFLAGS =
@ -45,7 +45,7 @@ LDFLAGS = -melf32lriscv_ilp32
$(LD) $(LDFLAGS) -T $^ -o $@ $(LD) $(LDFLAGS) -T $^ -o $@
%.hex: %.elf %.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@ riscv64-unknown-elf-objcopy --target=verilog $< $@
%.out: %.sv $(SOURCE_V) %.out: %.sv $(SOURCE_V)
iverilog -g2012 -o $@ $^ iverilog -g2012 -o $@ $^