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more clean up and reorganization from memory restructuring

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This commit is contained in:
Brendan Haines 2021-07-02 03:28:21 -06:00
parent 69e4ea9204
commit 57e745b336
2 changed files with 43 additions and 37 deletions
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25
hdl/tb/core_tb.gtkw
View File

@ -1,19 +1,19 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 09:02:34 2021
[*] Fri Jul 2 09:22:29 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Fri Jul 2 09:00:37 2021"
[dumpfile_size] 808881
[dumpfile_mtime] "Fri Jul 2 09:19:55 2021"
[dumpfile_size] 709401
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 656100
[timestart] 0
[size] 1920 1052
[pos] -1 -1
*-16.000000 728100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-20.000000 438000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289
[signals_width] 241
[signals_width] 277
[sst_expanded] 1
[sst_vpaned_height] 301
@200
@ -25,6 +25,7 @@ core_tb.reset
-
@22
core_tb.mem_data_addr[31:0]
core_tb.mem_data_idx[31:0]
core_tb.mem_data_rdata[31:0]
core_tb.mem_data_wdata[31:0]
@28
@ -35,9 +36,8 @@ core_tb.mem_inst_data[31:0]
@200
-
-DUT
@23
core_tb.dut.\regfile[0][31:0]
@22
core_tb.dut.\regfile[0][31:0]
core_tb.dut.\regfile[1][31:0]
core_tb.dut.\regfile[2][31:0]
core_tb.dut.\regfile[3][31:0]
@ -105,6 +105,7 @@ core_tb.dut.\regfile[27][31:0]
core_tb.dut.\regfile[28][31:0]
core_tb.dut.\regfile[29][31:0]
core_tb.dut.\regfile[30][31:0]
@23
core_tb.dut.\regfile[31][31:0]
@200
-
@ -175,9 +176,17 @@ core_tb.dut.r_ex_store
-
@22
core_tb.dut.r_mem_pc[31:0]
core_tb.dut.r_mem_alu_out[31:0]
@28
core_tb.dut.r_mem_load
core_tb.dut.r_mem_store
@200
-
@22
core_tb.dut.r_wb_pc[31:0]
core_tb.dut.r_wb_alu_out[31:0]
core_tb.dut.r_wb_load_data[31:0]
@28
core_tb.dut.r_wb_load
[pattern_trace] 1
[pattern_trace] 0

55
hdl/tb/core_tb.v
View File

@ -12,19 +12,14 @@ initial begin: dump
end
end
reg clk, reset;
wire dummy_out;
// Memory Parameters
localparam MEM_ROM_LENGTH = 2048 >> 2; // words
localparam MEM_LENGTH = MEM_ROM_LENGTH + 2048 >> 2; // words
localparam MEM_DATA_BASE = 32'h00000800;
localparam INST_NOP = 32'h00000013; // nop
localparam DATA_DEFAULT = 32'h00000000;
localparam DATA_INVALID = 32'hdeadbeef;
reg clk, reset;
// Memory
reg [31:0] mem [0:MEM_LENGTH-1];
initial $readmemh("text.hex", mem);
@ -32,7 +27,7 @@ initial $readmemh("text.hex", mem);
// Instruction Memory
wire [31:0] mem_inst_addr;
wire [31:0] mem_inst_idx = mem_inst_addr >> 2;
wire [31:0] mem_inst_data = mem_inst_idx < MEM_LENGTH ? mem[mem_inst_idx] : INST_NOP;
wire [31:0] mem_inst_data = mem_inst_idx < MEM_LENGTH ? mem[mem_inst_idx] : DATA_INVALID;
// Data memory
wire [31:0] mem_data_addr;
@ -42,6 +37,29 @@ wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
always @(posedge clk) begin
if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
if (mem_data_we) begin
if (mem_data_wmask[0]) begin
mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
end
if (mem_data_wmask[1]) begin
mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
end
if (mem_data_wmask[2]) begin
mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
end
if (mem_data_wmask[3]) begin
mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
end
end
end else begin
// ignore illegal writes
end
end
// Main control
initial begin
#0
clk = 0;
@ -137,25 +155,4 @@ core dut(
// .WB_RREADY()
// );
always @(posedge clk) begin
if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
if (mem_data_we) begin
if (mem_data_wmask[0]) begin
mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
end
if (mem_data_wmask[1]) begin
mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
end
if (mem_data_wmask[2]) begin
mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
end
if (mem_data_wmask[3]) begin
mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
end
end
end else begin
// ignore illegal writes
end
end
endmodule