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passes quick test: sll, srl, sra

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Brendan Haines 2020-10-16 18:25:10 -06:00
parent 913ffb3af6
commit 52a28d4e47
3 changed files with 51 additions and 1302 deletions
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6
hdl/core.v
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@ -309,13 +309,13 @@ always @(*) begin
s_ex_alu_out = s_ex_data1 & s_ex_data2; s_ex_alu_out = s_ex_data1 & s_ex_data2;
end end
ALUOP_SL: begin ALUOP_SL: begin
s_ex_alu_out = s_ex_data1 << s_ex_data2; s_ex_alu_out = s_ex_data1 << s_ex_data2[4:0];
end end
ALUOP_SRL: begin ALUOP_SRL: begin
s_ex_alu_out = s_ex_data1 >> s_ex_data2[5:0]; // NOTE: shamt is only 5 bits. Increased for gcc support s_ex_alu_out = s_ex_data1 >> s_ex_data2[4:0];
end end
ALUOP_SRA: begin ALUOP_SRA: begin
s_ex_alu_out = $signed(s_ex_data1) >>> s_ex_data2[5:0]; // NOTE: shamt is only 5 bits. Increased for gcc support s_ex_alu_out = $signed(s_ex_data1) >>> s_ex_data2[4:0];
end end
ALUOP_SLT: begin ALUOP_SLT: begin
s_ex_alu_out = $signed(s_ex_data1) < $signed(s_ex_data2); s_ex_alu_out = $signed(s_ex_data1) < $signed(s_ex_data2);

1295
sim/core_tb.wcfg
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File diff suppressed because it is too large Load Diff

52
test/test.S
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@ -11,9 +11,6 @@ _start:
# SLTI # SLTI
# SLTUI # SLTUI
# SLL
# SRL
# SRA
# SLT # SLT
# SLTU # SLTU
@ -96,7 +93,7 @@ _start:
# slli # slli
slli x24, x23, 4 # x24 = 0x00007880 slli x24, x23, 4 # x24 = 0x00007880
slli x25, x2, 1 # x25 = 0xfffffffe slli x25, x2, 1 # x25 = 0xfffffffe
slli x26, x2, 63 # x26 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b slli x26, x2, 63 # x26 = 0x80000000 # NOTE: gcc should not allow this since shamt is only 5 bits. discarding high bit so 63 = 31
slli x27, x2, 31 # x27 = 0x80000000 slli x27, x2, 31 # x27 = 0x80000000
nop nop
nop nop
@ -105,17 +102,54 @@ _start:
# srli # srli
srli x28, x23, 4 # x28 = 0x00000078 srli x28, x23, 4 # x28 = 0x00000078
srli x29, x2, 1 # x29 = 0x7fffffff srli x29, x2, 1 # x29 = 0x7fffffff
srli x30, x2, 63 # x30 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b srli x30, x2, 63 # x30 = 0x00000001 # NOTE: gcc should not allow this since shamt is only 5 bits. discarding high bit so 63 = 31
srli x3, x2, 31 # x3 = 0x00000001 srli x3, x2, 31 # x3 = 0x00000001
nop nop
nop nop
nop nop
# srai # srai
srai x4, x23, 4 # x4 = 0x00000078 // fails srai x4, x23, 4 # x4 = 0x00000078
srai x5, x2, 1 # x5 = 0xffffffff srai x5, x2, 1 # x5 = 0xffffffff
srai x6, x2, 63 # x6 = 0xffffffff // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b srai x6, x2, 63 # x6 = 0xffffffff # NOTE: gcc should not allow this since shamt is only 5 bits. discarding high bit so 63 = 31
srai x7, x2, 31 # x7 = 0xffffffff srai x7, x2, 31 # x7 = 0xffffffff
nop
nop
nop
# sll
addi x8, x0, 4 # x8 = 0x00000004
addi x9, x0, 1 # x9 = 0x00000001
addi x10, x0, 63 # x10 = 0x0000003f
addi x11, x0, 31 # x11 = 0x0000001f
sll x12, x23, x8 # x12 = 0x00007880 # 4
sll x13, x2, x9 # x13 = 0xfffffffe # 1
sll x14, x2, x10 # x14 = 0x80000000 # 63 = 31
sll x15, x2, x11 # x15 = 0x80000000 # 31
sll x16, x1, x0 # x16 = 0xfedcb789 # 0
sll x17, x1, x2 # x17 = 0x80000000 # -1=31
nop
nop
nop
# srl
srl x18, x23, x8 # x18 = 0x00000078 # 4
srl x19, x2, x9 # x17 = 0x7fffffff # 1
srl x20, x2, x10 # x20 = 0x00000001 # 63 = 31
srl x21, x2, x11 # x21 = 0x00000001 # 31
srl x22, x1, x0 # x22 = 0xfedcb789 # 0
srl x24, x1, x2 # x24 = 0x00000001 # -1=31
nop
nop
nop
# sra
sra x25, x23, x8 # x25 = 0x00000078 # 4
sra x26, x2, x9 # x26 = 0xffffffff # 1
sra x27, x2, x10 # x27 = 0xffffffff # 63 = 31
sra x28, x2, x11 # x28 = 0xffffffff # 31
sra x29, x1, x0 # x29 = 0xfedcb789 # 0
sra x30, x1, x2 # x30 = 0xffffffff # -1=31
nop nop
nop nop
nop nop