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use systemverilog 2012 for simulation

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Brendan Haines 2022-11-19 18:41:25 -07:00
parent 8055444b99
commit 449efd3c3c
2 changed files with 5 additions and 5 deletions
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8
tests/test_basic/Makefile
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@ -10,6 +10,7 @@ SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o)) OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o)) OBJ += $(notdir $(SOURCE_C:.c=.o))
# Software compilation
CC = riscv64-linux-gnu-gcc CC = riscv64-linux-gnu-gcc
CFLAGS = -march=rv32i -mabi=ilp32 CFLAGS = -march=rv32i -mabi=ilp32
@ -21,7 +22,6 @@ ASFLAGS = -march=rv32i -mabi=ilp32
LD = riscv64-linux-gnu-ld LD = riscv64-linux-gnu-ld
LDFLAGS = -melf32lriscv_ilp32 LDFLAGS = -melf32lriscv_ilp32
# $(info $$TESTBENCH_V is [${TESTBENCH_V}]) # $(info $$TESTBENCH_V is [${TESTBENCH_V}])
# $(info $$SOURCE_V is [${SOURCE_V}]) # $(info $$SOURCE_V is [${SOURCE_V}])
# $(info $$LOGS is [${LOGS}]) # $(info $$LOGS is [${LOGS}])
@ -29,7 +29,6 @@ LDFLAGS = -melf32lriscv_ilp32
# $(info $$SOURCE_AS is [${SOURCE_AS}]) # $(info $$SOURCE_AS is [${SOURCE_AS}])
# $(info $$OBJ is [${OBJ}]) # $(info $$OBJ is [${OBJ}])
%.o: %.S %.o: %.S
$(AS) $(ASFLAGS) $^ -o $@ $(AS) $(ASFLAGS) $^ -o $@
@ -43,9 +42,11 @@ LDFLAGS = -melf32lriscv_ilp32
%.hex: %.elf %.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@ riscv64-linux-gnu-objcopy --target=verilog $< $@
# Hardware compilation
%.out: %.sv $(SOURCE_V) %.out: %.sv $(SOURCE_V)
iverilog -o $@ $^ iverilog -g2012 -o $@ $^
# Run test
%.vcd %.log: %.out %.hex %.vcd %.log: %.out %.hex
./$< | tee $(patsubst %.out, %.log, $<) ./$< | tee $(patsubst %.out, %.log, $<)
@ -60,4 +61,3 @@ clean:
.SECONDARY: %.log %.vcd .SECONDARY: %.log %.vcd
.PHONY: all clean verify .PHONY: all clean verify

2
tests/test_c/Makefile
View File

@ -48,7 +48,7 @@ LDFLAGS = -melf32lriscv_ilp32
riscv64-linux-gnu-objcopy --target=verilog $< $@ riscv64-linux-gnu-objcopy --target=verilog $< $@
%.out: %.sv $(SOURCE_V) %.out: %.sv $(SOURCE_V)
iverilog -o $@ $^ iverilog -g2012 -o $@ $^
%.vcd %.log: %.out %.hex %.vcd %.log: %.out %.hex
./$< | tee $(patsubst %.out, %.log, $<) ./$< | tee $(patsubst %.out, %.log, $<)